US4356544A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for controlling an inverter main circuit
Assignee: Toshiba Corp
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Filing: 1981-05-29
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Granted: 1982-10-26
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Expires: 2001-05-29
Abstract
Abstract An apparatus for controlling an inverter main circuit has a memory circuit for storing digital control signals which correspond to 180°/n portions of output voltage waveforms of the inverter main circuit, where n is an integer. The memory circuit has a plurality of memory areas. One of the memory areas is designated by a digital signal supplied from a speed setting circuit. And the addresses of any memory area thus designated are designated by output signals of an up-down counter, one after another in ascending order of their serial numbers (forward direction) and in descending order of their serial numbers (backward direction). As they are designated, the memory regions corresponding to addresses supplies control signals. Every time the addressing direction is changed, the up-down counter generates a clock signal to a converter circuit which has 2n output terminals. In response to the clock signal supplied from the up-down counter, the converter circuit supplies signals to a waveform synthesizer circuit, one after another via the 2n output terminals. According to the signals from the converter circuit the waveform synthesizer circuit supplies to the inverter main circuit the control data in a predetermined order.
Inventors
- 👤 Takuo Ono
- 👤 Sigeo Fukui
- 👤 Junichi Ookura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:42
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/08; H02M1/084; H02M1/0845; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5387; H02M7/53871; H02M7/53873
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
268 words
An apparatus for controlling an inverter main circuit, comprising: an output setting circuit for generating digital signals determining the output frequency of an inverter main circuit; a memory circuit connected to the output setting circuit for storing control signals having logic patterns which correspond to the frequencies represented by the digital signals, said control signals each corresponding to a 180°/n portion of the output voltage waveform of the inverter main circuit, where n is a positive integer; a correcting circuit connected to the output setting circuit for generating, according to the digital signals, a first clock signal which makes the output voltage of the inverter main circuit have a predetermined relation with the frequency represented by the digital signals; an up-down counter connected to the correcting circuit for counting up and down the first clock signals and reading the control signals from the memory circuit in ascending and descending sequences of address numbers of the memory circuit, thereby generating a second clock signal every time the counting direction is reversed; a converter connected to the up-down counter for generating a signal in response to the second clock signal, said converter having 2n output terminals from which one signal after another is supplied; and a waveform synthesizer circuit connected to the memory circuit and the converter for supplying to the inverter main circuit some of the control signals read from the memory circuit in a predetermined order, every time the inverter main circuit generates a 180°/n portion of the output voltage waveform and in accordance with the signals supplied one after another from the output terminals of the converter.
Claim 2
Independent Claim
268 words
An apparatus for controlling an inverter main circuit, comprising: an output setting circuit for generating digital signals determining the output frequency of an inverter main circuit; a memory circuit connected to the output setting circuit for storing control signals having logic patterns which correspond to the frequencies represented by the digital signals, said control signals each corresponding to a 180°/n portion of the output voltage waveform of the inverter main circuit, where n is a positive integer; a correcting circuit connected to the output setting circuit for generating, according to the digital signals, a first clock signal which makes the output voltage of the inverter main circuit have a predetermined relation with the frequency represented by the digital signals; an up-down counter connected to the correcting circuit for counting up and down the first clock signals and reading the control signals from the memory circuit in ascending and descending sequences of address numbers of the memory circuit, thereby generating a second clock signal every time the counting direction is reversed; a converter connected to the up-down counter for generating a signal in response to the second clock signal, said converter having 2n output terminals from which one signal after another is supplied; and a waveform synthesizer circuit connected to the memory circuit and the converter for supplying to the inverter main circuit some of the control signals read from the memory circuit in a predetermined order, every time the inverter main circuit generates a 180°/n portion of the output voltage waveform and in accordance with the signals supplied one after another from the output terminals of the converter.
Claim 3
Dependent Claim
121 words
An apparatus according to claim 1, wherein said memory circuit comprises a ROM connected to said output setting circuit and said up-down counter, said ROM having a plurality of memory areas which are designated by digital signals supplied from said output setting circuit and the addresses of which are designated by signals supplied from said up-down counter; a data selector connected to the ROM and said output setting circuit for selecting, according to a signal supplied from said output setting circuit, some of the bits stored in an address designated by signals supplied from said up-down counter and read these bits from said memory circuit; and inverter circuits connected to the data selector for inverting the outputs of the data selector.
Claim 4
Dependent Claim
98 words
An apparatus according to claim 1, wherein said up-down counter comprises an up-down counter section connected to said correcting circuit for counting first clock signals and supplying address designating signals to said memory circuit; a detector section connected to the up-down counter section for detecting the change of counting mode; a flip-flop connected to the detector section and set and reset according to an output signal of the detector section, thereby supplying a count-up signal and a count-down signal to the up-down counter; and a circuit connected to the detector section for supplying second signals to said converter.
Claim 5
Dependent Claim
54 words
An apparatus according to claim 1, wherein said waveform synthesizer circuit comprises a waveform synthesizer connected to said memory circuit and said converter for supplying in a predetermined order the control signals read from said memory circuit and inverter circuits connected to the waveform synthesizer for inverting the output signals of the waveform synthesizer.
References Cited (Backward Citations)
US4290108A
Cited
US4312031A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-10-25 | 1986-04-26 | 1986-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-10-25 | 1990-04-26 | 1990-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-10-25 | 1994-04-26 | 1994-10-26 | $7700.00 | Window Closed / Lapsed |