US4356389A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bar code scanner interface
Assignee: Motorola Solutions Inc
•
Filing: 1980-06-27
•
Granted: 1982-10-26
•
Expires: 2000-06-27
Abstract
Abstract The positive and negative peak detectors in the interface are reset during each input signal cycle and the reference level used for comparison is switched from one level to another to improve decoding accuracy, with each level determined by the previous two peaks. The input signal is DC coupled and DC offset. The scanner light source is pulsed by a low duty cycle power source if code is not being scanned. The circuit is applicable for digitizing any analog signal with varying amplitudes and/or DC levels and is adaptable to microprocessor control.
Inventors
- 👤 Tim A. Quirey
- 👤 Thomas V. D'Amico
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:27
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/10; G06K7/10544; G06K7/10821; G06K7/10881; G06K7/14; G06K2207/00; G06K2207/1018
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
141 words
An interface circuit as for a bar code scanner and comprising: DC coupled input means for receiving a signal varying in DC level and peak values; positive peak detector means coupled to the input means; negative peak detector means coupled to the input means; reset means coupled to reset the peak detectors during each signal cycle, one after each signal transition; switchable reference means coupled to the positive and negative peak detector means outputs for providing a reference signal having an instantaneous value equal to the last detected peak value summed with a fixed fraction of the difference between the last detected peak value and the presently detected peak value, said fixed fraction being substantially greater than one-half; comparator means coupled to the outputs of the input means and the switchable reference means; and output means coupled to the comparator means.
Claim 2
Dependent Claim
141 words
An interface circuit as for a bar code scanner and comprising: DC coupled input means for receiving a signal varying in DC level and peak values; positive peak detector means coupled to the input means; negative peak detector means coupled to the input means; reset means coupled to reset the peak detectors during each signal cycle, one after each signal transition; switchable reference means coupled to the positive and negative peak detector means outputs for providing a reference signal having an instantaneous value equal to the last detected peak value summed with a fixed fraction of the difference between the last detected peak value and the presently detected peak value, said fixed fraction being substantially greater than one-half; comparator means coupled to the outputs of the input means and the switchable reference means; and output means coupled to the comparator means.
Claim 3
Dependent Claim
55 words
An interface circuit in accordance with claim 1 wherein the switchable reference means includes a resistive network, an output terminal and a voltage-controlled switch, coupled to vary the voltage at the output terminal as a function of the output voltages at the peak detector outputs, the switch being controlled by the last signal transition detected.
Claim 4
Dependent Claim
28 words
An interface circuit in accordance with claim 1 and wherein the input means includes amplifier means for amplifying and adding a DC offset signal to the input signal.
Claim 5
Dependent Claim
19 words
An interface circuit in accordance with claim 3 wherein the input means further includes sample-and-hold means and switching means.
Claim 6
Dependent Claim
21 words
An interface circuit in accordance with claim 4 wherein the switching means is controlled in response to the input signal characteristics.
Claim 7
Dependent Claim
21 words
An interface circuit in accordance with claim 5 wherein said signal characteristics include level of signal and time between signal transitions.
Claim 8
Dependent Claim
30 words
An interface circuit in accordance with claim 5 and further including second switching means responsive to the input signal characteristics for pulsing an external circuit at a low duty cycle.
Claim 9
Dependent Claim
32 words
An interface circuit in accordance with claim 1 and further including hysteresis means coupled to the outputs of the peak detector means for providing a symmetrical hysteresis signal to the comparator means.
References Cited (Backward Citations)
US3225213A
Cited
US3991299A
Cited
US3909594A
Cited
US3925639A
Cited
US4013893A
Cited
US4240064A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-10-25 | 1986-04-26 | 1986-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-10-25 | 1990-04-26 | 1990-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-10-25 | 1994-04-26 | 1994-10-26 | $7700.00 | Window Closed / Lapsed |