Resolver processor with error detection

Claim 2

A processor for converting the angular position of a resolver into a digital representation thereof in response to a conversion request, wherein the resolver generates a pair of resolver signals as a function of the angular position of the resolver and valid resolver signals are limited to a predetermined range of angular position by physically restraining the resolver rotation to said range, said processor comprising: means, responsive to the resolver signals, for generating a pair of phase shifted signals with a relative phase shift proportional to the resolver angle; means for converting the relative phase shift between said phase shifted signals to said digital representations of the resolver angle; and means for indicating fault conditions in the resolver signals by generating digital representations of angular positions outside said predetermined range.

Claim 3

The processor of claim 1, wherein: said phase shifted signal generating means includes means for generating a leading signal in response to one of the resolver signals, and means for generating a lagging signal in response to the other of the resolver signals, the relative time delay between the leading and lagging signals indicative of said relative phase shift between the phase shifted signals; and said converting means including a counter, means for enabling the counter in response to the leading signal and means for inhibiting the counter in response to the lagging signal so that the contents of the counter represents the relative phase shift.

Claim 4

A processor as defined in claim 1, wherein: said predetermined range is for resolver angles greater than 45° and less than or equal to 225°.

Claim 5

A processor as defined in claim 1, wherein: said predetermined range is for resolver angles greater than 90° and less than or equal to 225°.

Claim 6

The resolver processor of claim 2, further comprising: means for generating an overflow signal when the contents of the counter overflows when no lagging signal inhibits the counter after the counter has been enabled by a leading signal, said fault indicating means being responsive to said overflow signal to generate a digital representation of an angular position outside said predetermined range.

Claim 7

The resolver processor of claim 5, further comprising: storage means for storing the digital representations contained in the counter in response to a latch signal.

Claim 8

The resolver processor of claim 6, further comprising: means for generating said latch signal followed by a clear signal when the leading signal and the lagging signal are in selected states.

Claim 9

The resolver processor of claim 2, said fault indicating means further comprising: means responsive to the conversion request for generating an error signal when no leading signal occurs within a predetermined time interval after the conversion request.

Claim 10

The resolver processor of claim 8, said fault indicating means further comprising: means responsive to the error signal for generating a clear signal to said counter followed by a latch signal, said clear signal clearing the contents of said counter to zero wherein such number is a digital representation of an angular position outside said predetermined range.

Claim 11

The resolver processor of claim 9, further comprising: storage means for storing the angle representations contained in the counter in response to the latch signal.

Claim 12

A processor as efined in claim 3, wherein: said representation of a resolver angle outside said predetermined range is a representation of a resolver angle of 45°.

Claim 13

A processor as defined in claim 3, wherein: said representation of a resolver angle outside said predetermined range includes a representation of a resolver angle of 90°.

Claim 14

A processor as defined in claim 4, wherein: said predetermined range is for resolver angles greater than 90° and less than 180°.

Claim 15

A processor as defined in claim 13, wherein: said representations of a resolver angle outside said predetermined range includes a representation of resolver angle of 180°.

Claim 16

A processor as defined in claim 14, wherein: said representations of a resolver angle outside said predetermined range includes a representation of a resolver angle of 45°.

Claim 17

A resolver processor system comprising: an angle resolver physically restrained to move between angles of θ greater than 90° and less than 180°, said resolver generating a pair of resolver signals, V sin (2πft) cos θ, V sin (2πft) sin θ, where V is the amplitude of the resolver signals, f is the frequency of the resolver signals, and θ is the angular position of the resolver; means, receiving said resolver signals, for generating a pair of phase shifted signals, V sin (2πf-45°+θ), V sin (2πf+45°-θ), from said resolver signals, said phase shifted signals having a time delay between their zero crossings proportional to said phase shift and said angular position; means for detecting the zero crossing of one of said phase shifted signals and for generating a start signal in response thereto; means for detecting the zero rossing of the other of said phase shifted signals and for generating a stop signal in response thereto; a counter with a clock input, clear input, an overflow output, and counter outputs, said counter operably incremented by a clock signal applied to its clock input and cleared by a clear signal applied to its clear input; count control means enabled in response to a conversion request for gating said clock signal to said counter in response to said start signal, for inhibiting said clock signal to said counter in response to said stop signal, and for generating a conversion finish signal in response to said sto signal only when preceeded by a start signal, wherein the output of said counter is a digital representation of the phase shift between the two phase shifted signals and proportional to θ; said digital counter having a minimum or zero count assigned to conditions where said phase shifted signals are in phase and a maximum count assigned to conditions where said phase shifted signals are 180° out of phase, wherein said restrained resolver angles define a predetermined range of valid digital representations of said counter; a data latch connected to the outputs of said counter for holding the digital representations of the counter, said latch having a clock input and being operable to transfer said digital representations from said counter outputs to said latch in response to a latch signal applied to its clock input; means responsive to a conversion finish signal for generating a latch signal to said latch and, after said latch receives said digital representation, for then generating a clear signal to said counter; means for generating said conversion finish signal in response to an overflow signal from the counter overflow output when no stop signal inhibits the counter after the counter has been gated by a start signal, wherein said data latch contains a digital representation which is outside said predetermined range and is an indication of a fault condition; and means for generating clear signal to said counter and thereafter said conversion finish signal when no start signal occurs within a predetermined time interval after said conversion request, wherein said data latch contains a digital representation which is outside said predetermined range and is an indication of a fault condition.

Claim 18

A resolver processor system comprising: an angle resolver physically restrained to move between angles of θ greater than 90° and less than 180°, said resolver generating a pair of resolver signals, V sin (2πft) cos θ, V sin (2πft) sin θ, where V is the amplitude of the resolver signals, f is the frequency of the resolver signals, and θ is the angular position of the resolver; means, receiving said resolver signals, for generating a pair of phase shifted signals, V sin (2πf-45°+θ), V sin (2πf+45°-θ), from said resolver signals, said phase shifted signals having a time delay between their zero crossings proportional to said phase shift and said angular position; means for detecting the zero crossing of one of said phase shifted signals and for generating a start signal in response thereto; means for detecting the zero rossing of the other of said phase shifted signals and for generating a stop signal in response thereto; a counter with a clock input, clear input, an overflow output, and counter outputs, said counter operably incremented by a clock signal applied to its clock input and cleared by a clear signal applied to its clear input; count control means enabled in response to a conversion request for gating said clock signal to said counter in response to said start signal, for inhibiting said clock signal to said counter in response to said stop signal, and for generating a conversion finish signal in response to said sto signal only when preceeded by a start signal, wherein the output of said counter is a digital representation of the phase shift between the two phase shifted signals and proportional to θ; said digital counter having a minimum or zero count assigned to conditions where said phase shifted signals are in phase and a maximum count assigned to conditions where said phase shifted signals are 180° out of phase, wherein said restrained resolver angles define a predetermined range of valid digital representations of said counter; a data latch connected to the outputs of said counter for holding the digital representations of the counter, said latch having a clock input and being operable to transfer said digital representations from said counter outputs to said latch in response to a latch signal applied to its clock input; means responsive to a conversion finish signal for generating a latch signal to said latch and, after said latch receives said digital representation, for then generating a clear signal to said counter; means for generating said conversion finish signal in response to an overflow signal from the counter overflow output when no stop signal inhibits the counter after the counter has been gated by a start signal, wherein said data latch contains a digital representation which is outside said predetermined range and is an indication of a fault condition; and means for generating clear signal to said counter and thereafter said conversion finish signal when no start signal occurs within a predetermined time interval after said conversion request, wherein said data latch contains a digital representation which is outside said predetermined range and is an indication of a fault condition.