Processing unit for multiplying two mathematical quantities including at least one complex multiplier

Claim 2

A digital processing unit for multiplying two N-component mathematical quantities, X and Y, wherein each component is represented by an m bit digital word representative of a real portion and an m bit digital word representative of an imaginary portion, said unit comprising: (a) N complex multipliers each having an X input and a Y input, each input having m leads adapted to receive the real portion in parallel and m leads adapted to receive the imaginary portion in parallel, and an output having at least m+1 leads for the real portion and at least m+1 leads for the imaginary portion; (b) real portion summing means connected to the m+1 leads for the real portion at the output of each of said N complex multipliers for providing a real output component including at least m+2 parallel bits representative of the sum of the real portions from each of said complex multipliers; and (c) imaginary portion summing means connected to the m+1 leads for the imaginary portion at the output of each of said N complex multipliers for providing an imaginary output component including at least m+2 parallel bits representative of the sum of the imaginary portions from each of said complex multipliers.

Claim 3

A digital processing unit as claimed in claim 1 wherein the N-component mathematical quantities, X and Y, are applied to each of the X and Y inputs of the N complex multipliers by means of a single 2mN-lead bus which first brings in X and latches it into the individual multipliers and subsequently Y.

Claim 4

A digital processing unit as claimed in claim 1 wherein each of the N-complex multipliers includes four multiplier circuits, the real and imaginary portions of the X and Y components being defined by the statements X=(A+jB) and Y=(C+jD), with the multiplier circuits being connected to provide the products AC, BD, AD and BC at the outputs thereof, and two combining circuits connected to the four multiplier circuits to provide m+1 bit output words representative of the statements (AC-BD) and j(BC+AD) respectively.

Claim 5

A digital processing unit as claimed in claim 3 wherein the two combining circuits include switching apparatus for controlling the manner of combining the input words to provide m+1 bit output words representative of the statements (AC+BD) and j(BC-AD) when properly activated.

Claim 6

A digital processing unit for multiplying two mathematical quantities, X and Y, wherein the number X is represented by an m bit digital word, A, representative of a real portion of an m bit digital word, jB, representative of an imaginary portion of the number Y is represented by an m bit digital word, C, representative of a real portion and an m bit digital word, jD, representative of an imaginary portion, the processing unit comprising: (a) four multiplier circuits connected to receive the m bit digital words and provide output words representative of the products AC, BD, AD and BC, respectively; (b) real portion combining circuitry connected to two of said four multiplier circuits to receive the products AC and BD and provide at least an m+1 bit output word representative of the statement (AC-BD); (c) imaginary portion combining circuitry connected to the remaining two of said four multiplier circuits to receive the products AD and BC and provide at least an m+1 bit output word representative of the statement j(BC+AD); and (d) switching apparatus included in said real portion and imaginary portion combining circuitry for controlling the manner of combining the input signals to provide m+1 bit output words representative of the statements (AC+BD) and j(BC-AD) when properly activated.

Claim 7

A digital processing unit for multiplying two mathematical quantities, X and Y, wherein the number X is represented by an m bit digital word, A, representative of a real portion of an m bit digital word, jB, representative of an imaginary portion of the number Y is represented by an m bit digital word, C, representative of a real portion and an m bit digital word, jD, representative of an imaginary portion, the processing unit comprising: (a) four multiplier circuits connected to receive the m bit digital words and provide output words representative of the products AC, BD, AD and BC, respectively; (b) real portion combining circuitry connected to two of said four multiplier circuits to receive the products AC and BD and provide at least an m+1 bit output word representative of the statement (AC-BD); (c) imaginary portion combining circuitry connected to the remaining two of said four multiplier circuits to receive the products AD and BC and provide at least an m+1 bit output word representative of the statement j(BC+AD); and (d) switching apparatus included in said real portion and imaginary portion combining circuitry for controlling the manner of combining the input signals to provide m+1 bit output words representative of the statements (AC+BD) and j(BC-AD) when properly activated.

Claim 8

A processing unit for multiplying two methematical quantities, X and Y, wherein the quantity X is represented by an electrical signal, A, representative of a real portion and an electrical signal jB, representative of an imaginary portion and the quantity Y is represented by an electrical signal C, representative of a real portion, and an electrical signal jD, representative of an imaginary portion, the processing unit comprising: (a) four multiplier circuits connected to receive the electrical signals and provide output signals representative of the products AC, BD, AD and BC, respectively; (b) real portion combining circuitry connected to two of said four multiplier circuits to receive the product signals AC and BD and provide an output signal representative of the statement (AC-BD); (c) imaginary portion combining circuitry connected to the remaining two of said four multiplier circuits to receive the product signals AD and BC and provide an output signal representative of the statement j(BC+AD); and (d) switching apparatus included in said real portion and imaginary portion combining circuitry for controlling the manner of combining the input signals to provide output signals representative of the statements (AC+BD) and j(BC-AD) when properly activated.

Claim 9

A processing unit for multiplying two methematical quantities, X and Y, wherein the quantity X is represented by an electrical signal, A, representative of a real portion and an electrical signal jB, representative of an imaginary portion and the quantity Y is represented by an electrical signal C, representative of a real portion, and an electrical signal jD, representative of an imaginary portion, the processing unit comprising: (a) four multiplier circuits connected to receive the electrical signals and provide output signals representative of the products AC, BD, AD and BC, respectively; (b) real portion combining circuitry connected to two of said four multiplier circuits to receive the product signals AC and BD and provide an output signal representative of the statement (AC-BD); (c) imaginary portion combining circuitry connected to the remaining two of said four multiplier circuits to receive the product signals AD and BC and provide an output signal representative of the statement j(BC+AD); and (d) switching apparatus included in said real portion and imaginary portion combining circuitry for controlling the manner of combining the input signals to provide output signals representative of the statements (AC+BD) and j(BC-AD) when properly activated.