US4354175A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog/digital converter utilizing a single column of analog switches
Assignee: STMicroelectronics lnc USA
•
Filing: 1980-05-01
•
Granted: 1982-10-12
•
Expires: 2000-05-01
Abstract
Abstract An analog switch for an analog-to-digital converter which permits an analog voltage level to be read from a series resistor ladder network and be compared to an external analog signal by a comparator. The incremental levels of the series resistor ladder network are selected by a tree decoder responsive to the comparator output. The analog switch has two transistors, the first transistor being connected between the resistor ladder network and the comparator and being gated by a second transistor and the tree decoder so that the first transistor may be precharged or accessed by the tree decoder.
Inventors
- 👤 Ira L. Goldstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:17
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
232 words
A method for converting an analog signal to a digital voltage level comprising: inputting high and low reference voltages to a series resistor ladder network having incremental levels; comparing the analog signal and the center incremental voltage level of the resistor ladder network; selecting an incremental level midway between the center incremental level and the high reference voltage or the low reference voltage depending on whether the analog signal voltage level is greater or lesser, respectively, than the center incremental voltage level; comparing the analog signal to the selected incremental voltage level; repeating the selection of an incremental voltage level and comparison of the analog signal and selected incremental voltage level until the incremental voltage levels are exhausted whereby the incremental voltage level nearest the analog signal to voltage level is determined; precharging with a voltage level a gate terminal of a plurality of series field effect transistors coupled between each incremental voltage level and a comparator such that each of the field effect transistors is in the off state; removing the precharging voltage at the gates of the plurality of series field effect transistors when a decode tree, coupled to the gates of the plurality of field effect transistors, enables one of the plurality of series field effect transistors; and holding the unselected series field effect transistors off by the remnants of the precharge voltage held by the respective gate capacitances.
Claim 2
Independent Claim
232 words
A method for converting an analog signal to a digital voltage level comprising: inputting high and low reference voltages to a series resistor ladder network having incremental levels; comparing the analog signal and the center incremental voltage level of the resistor ladder network; selecting an incremental level midway between the center incremental level and the high reference voltage or the low reference voltage depending on whether the analog signal voltage level is greater or lesser, respectively, than the center incremental voltage level; comparing the analog signal to the selected incremental voltage level; repeating the selection of an incremental voltage level and comparison of the analog signal and selected incremental voltage level until the incremental voltage levels are exhausted whereby the incremental voltage level nearest the analog signal to voltage level is determined; precharging with a voltage level a gate terminal of a plurality of series field effect transistors coupled between each incremental voltage level and a comparator such that each of the field effect transistors is in the off state; removing the precharging voltage at the gates of the plurality of series field effect transistors when a decode tree, coupled to the gates of the plurality of field effect transistors, enables one of the plurality of series field effect transistors; and holding the unselected series field effect transistors off by the remnants of the precharge voltage held by the respective gate capacitances.
Claim 3
Dependent Claim
236 words
An analog-to-digital converter for converting an analog signal to a digital level comprising: a first and a second reference voltage terminal; a series resistor ladder network connected between the first and second reference voltage terminals and having a plurality of taps at incremental voltage levels; A switch array coupled between the taps of the ladder network and a common output terminal and having a like plurality of analog switches for detecting an incremental voltage in the resistor ladder network; a digital decode tree coupled to the switch array for selecting a single analog switch in the switch array; the analog switches comprised of a series field effect transistor having drain, source and gate terminals, the source terminal coupled to one of the plurality of taps, the drain terminal coupled to the common output terminal, the gate terminal coupled to the digital decode tree, and means for precharging the gate terminal at a time when the digital decode tree is not selecting a single analog switch in the switch array; a comparator for receiving the analog signal and the signal at the common output terminal and producing an output determined by the difference in the analog signal and signal at the common output terminal; and means responsive to the comparator output and logically controlling the decode tree selection of analog switches in the switch array whereby the incremental voltage level approximating the analog signal may be determined.
Claim 4
Dependent Claim
236 words
An analog-to-digital converter for converting an analog signal to a digital level comprising: a first and a second reference voltage terminal; a series resistor ladder network connected between the first and second reference voltage terminals and having a plurality of taps at incremental voltage levels; A switch array coupled between the taps of the ladder network and a common output terminal and having a like plurality of analog switches for detecting an incremental voltage in the resistor ladder network; a digital decode tree coupled to the switch array for selecting a single analog switch in the switch array; the analog switches comprised of a series field effect transistor having drain, source and gate terminals, the source terminal coupled to one of the plurality of taps, the drain terminal coupled to the common output terminal, the gate terminal coupled to the digital decode tree, and means for precharging the gate terminal at a time when the digital decode tree is not selecting a single analog switch in the switch array; a comparator for receiving the analog signal and the signal at the common output terminal and producing an output determined by the difference in the analog signal and signal at the common output terminal; and means responsive to the comparator output and logically controlling the decode tree selection of analog switches in the switch array whereby the incremental voltage level approximating the analog signal may be determined.
Claim 5
Dependent Claim
53 words
The analog-to-digital converter of claim 2 wherein the means for precharging the gate terminal comprises: a second field effect transistor having its drain connected to the gate of the series field effect transistor and to the decoder tree, its source connected to a supply voltage, and its gate connected to a precharge signal.
References Cited (Backward Citations)
US4045793A
Cited
GB2029658A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-10-11 | 1986-04-12 | 1986-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-10-11 | 1990-04-12 | 1990-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-10-11 | 1994-04-12 | 1994-10-12 | $7700.00 | Window Closed / Lapsed |