Battery operated access control card

Claim 2

An access control card used in access control systems comprising: a battery; wireless signal receiving means for receiving a coded wireless signal generated by a card reader; clock means connected to the battery and including a receiver connected to the antenna for supplying a received signal based upon said coded wireless signal; memory means for storing first and second stored codes; and, transmit means connected to said wireless signal receiving means, to said clock means and to said memory means for comparing said first stored code and said received signal and for transmitting said second stored code when there is a match between said received signal and said first stored code.

Claim 3

The card of claim 1 wherein said transmit means comprises comparator means for providing a mismatch signal when said received signal and said first stored code do not match, and said clock means comprises a clock and clock enable means responsive to said mismatch signal for terminating operation of said clock.

Claim 4

The card of claim 2 wherein said memory means comprises a counter responsive to said clock for providing addresses and a memory circuit responsive to said addresses for supplying said first stored code to said comparator means, said clock continuing to drive said address counter if said received signal has been successfully compared to said first stored code and for interrupting said counter if said first stored code is not successfully compared to said received signal.

Claim 5

The card of claim 3 wherein said counter has a plurality of outputs and said memory means further comprises a decoder circuit for decoding selected outputs of said counter for enabling said transmit means to transmit said second stored code only during a transmit mode, said transmit mode only occurring after the first stored code has been compared to the received signal.

Claim 6

The card of claim 4 wherein said memory means comprises an end of cycle decoder connected to selected outputs of said counter for providing an end of cycle signal after said second stored code has been supplied by said memory means to said transmit means, said end of cycle signal resetting said clock enable means to interrupt said clock.

Claim 7

The card of claim 5 wherein said clock comprises an oscillator responsive to said clock enable means for providing an output and a counter-decoder circuit responsive to said output from said oscillator to drive said counter of said address means.

Claim 8

The card of claim 6 wherein said clock enable means comprises flip-flop means responsive to the beginning of said received signal for energizing said clock and responsive to said end of cycle signal and said mismatch signal for terminating operation of said clock.

Claim 9

The card of claim 1 wherein said memory means comprises a counter responsive to said clock means for providing addresses and a memory circuit responsive to said addresses for supplying said first stored code to said transmit means, said clock means continuing to drive said address counter if said received signal and said first stored code have been successfully compared by said transmit means and for interrupting said address counter if said first stored code is not successfully compared to said received signal.

Claim 10

The card of claim 8 wherein said counter has a plurality of outputs and said memory means further comprises a decoder circuit for decoding selective outputs of said address counter for enabling said transmit means to transmit said second stored code only during a transmit mode, said transmit mode only occurring after the first stored code has been compared to the received signal.

Claim 11

The card of claim 9 wherein said memory means comprises an end of cycle decoder connected to selected outputs for said counter for providing an end of cycle signal after said second stored code has been supplied by said memory means to said transmit means, said end of cycle signal resetting said clock means to interrupt said clock means.

Claim 12

The card of claim 10 wherein said clock means comprises an oscillator for providing an output and a counter-decoder circuit responsive to said output from said oscillator to drive said counter of said address means.

Claim 13

The card of claim 1 wherein said memory means comprises a counter driven by said clock means and having a plurality of outputs, and a decoder circuit for decoding selected outputs of said counter for enabling said transmit means to transmit said second stored code only during a transmit mode, said transmit mode only occurring after the first stored code and said received signal have been compared by said transmit means.

Claim 14

The card of claim 12 wherein said memory means comprises an end of cycle decoder connected to selected outputs from said counter for providing an end of cycle signal after said second stored code has been supplied by said memory means to said transmit means, said end of cycle signal resetting said clock means to interrupt said clock means.

Claim 15

The card of claim 13 wherein said clock means comprises an oscillator for providing an output and a counter-decoder circuit responsive to said output from said oscillator to drive said counter of said address means.

Claim 16

The card of claim 1 wherein said wireless signal receiving means comprises an antenna and said coded wireless signal comprises a coded radio frequency signal.

Claim 17

The card of claim 15 wherein said transmit means comprises comparator means for providing a mismatch signal when said received signal and said first stored code do not match, and said clock means comprises a clock and clock enable means responsive to said mismatch signal for terminating operation of said clock.

Claim 18

The card of claim 16 wherein said memory means comprises a counter responsive to said clock for providing addresses and a memory circuit responsive to said addresses for supplying said first stored code to said comparator means, said clock continuing to drive said address counter if said received signal has been successfully compared to said first stored code and for interrupting said counter if said first stored code is not successfully compared to said received signal.

Claim 19

The card of claim 17 wherein said counter has a plurality of outputs and said memory means further comprises a decoder circuit for decoding selected outputs of said counter for enabling said transmit means to transmit said second stored code only during a transmit mode, said transmit mode only occurring after the first stored code has been compared to the received signal.

Claim 20

The card of claim 18 wherein said memory means comprises an end of cycle decoder connected to selected outputs of said counter for providing an end of cycle signal after said second stored code has been supplied by said memory means to said transmit means, said end of cycle signal resetting said clock enable means to interrupt said clock.

Claim 21

The card of claim 19 wherein said clock comprises an oscillator responsive to said clock enable means for providing an output and a counter-decoder circuit responsive to said output from said oscillator to drive said counter of said address means.

Claim 22

The card of claim 20 wherein said clock enable means comprises flip-flop means responsive to the beginning of said received signal for energizing said clock and responsive to said end of cycle signal and said mismatch signal for terminating operation of said clock.

Claim 23

The card of claim 15 wherein said memory means comprises a counter responsive to said clock means for providing addresses and a memory circuit responsive to said addresses for supplying said first stored code to said transmit means, said clock means continuing to drive said address counter if said received signal and said first stored code have been successfully compared by said transmit means and for interrupting said address counter if said first stored code is not successfully compared to said received signal.

Claim 24

The card of claim 22 wherein said counter has a plurality of outputs and said memory means further comprises a decoder circuit for decoding selective outputs of said address counter for enabling said transmit means to transmit said second stored code only during a transmit mode, said transmit mode only occurring after the first stored code has been compared to the received signal.

Claim 25

The card of claim 23 wherein said memory means comprises an end of cycle decoder connected to selected outputs for said counter for providing an end of cycle signal after said second stored code has been supplied by said memory means to said transmit means, said end of cycle signal resetting said clock means to interrupt said clock means.

Claim 26

The card of claim 24 wherein said clock means comprises an oscillator for providing an output and a counter-decoder circuit responsive to said output from said oscillator to drive said counter of said address means.

Claim 27

The card of claim 15 wherein said memory means comprises a counter driven by said clock means and having a plurality of outputs, and a decoder circuit for decoding selected outputs of said counter for enabling said transmit means to transmit said second stored code only during a transmit mode, said transmit mode only occurring after the first stored code and said received signal have been compared by said transmit means.

Claim 28

The card of claim 26 wherein said memory means comprises an end of cycle decoder connected to selected outputs from said counter for providing an end of cycle signal after said second stored code has been supplied by said memory means to said transmit means, said end of cycle signal resetting said clock means to interrupt said clock means.

Claim 29

The card of claim 27 wherein said clock means comprises an oscillator for providing an output and a counter-decoder circuit responsive to said output from said oscillator to drive said counter of said address means.

Claim 30

An access control card used in access control systems comprising: a battery; an antenna for receiving a coded radio frequency signal generated by a card reader; a receiver connected to said antenna and to said battery for supplying a received signal based upon said coded radio frequency signal; a clock connected to said receiver and to said battery for supplying a clock signal upon receipt by the receiver of said coded radio frequency signal; memory means connected to said clock for storing first and second stored codes and for supplying said first and second stored codes to an output of said memory means in response to said clock signal; comparator means connected to said output of said memory means and connected to said receiver for comparing said first stored code to said received signal and connected to said clock means for terminating said clock signal when there is a mismatch between said first stored code and said received signal; and, transmit means connected to said antenna, to said clock means and to said memory means for transmitting said second stored code after said first stored code has been successfully compared to said received signal.

Claim 31

An access control card used in access control systems comprising: a battery; an antenna for receiving a coded radio frequency signal generated by a card reader; a receiver connected to said antenna and to said battery for supplying a received signal based upon said coded radio frequency signal; a clock connected to said receiver and to said battery for supplying a clock signal upon receipt by the receiver of said coded radio frequency signal; memory means connected to said clock for storing first and second stored codes and for supplying said first and second stored codes to an output of said memory means in response to said clock signal; comparator means connected to said output of said memory means and connected to said receiver for comparing said first stored code to said received signal and connected to said clock means for terminating said clock signal when there is a mismatch between said first stored code and said received signal; and, transmit means connected to said antenna, to said clock means and to said memory means for transmitting said second stored code after said first stored code has been successfully compared to said received signal.

Claim 32

The card of claim 29 wherein said clock means comprises a clock and clock enable means responsive to said comparator means for terminating operation of said clock when there is a mismatch between said first stored code and said received signal.

Claim 33

The card of claim 30 wherein said memory means comprises a counter responsive to said clock for providing addresses and a memory circuit responsive to said addresses for supplying said first stored code to said comparator means, said clock continuing to drive said counter if said received signal has been successfully compared to said first stored code and for interrupting said counter if said first stored code is not successfully compared to said received signal.

Claim 34

The card of claim 31 wherein said counter has a plurality of outputs and said memory means further comprises a decoder circuit for decoding selected outputs of said counter for enabling said transmit means to transmit said second stored code only during a transmit mode, said transmit mode only occurring after the first stored code has been compared to the received signal.

Claim 35

The card of claim 32 wherein said memory means comprises an end of cycle decoder connected to selected outputs of said counter for providing an end of cycle signal after said second stored code has been supplied by said memory means to said transmit means, said end of cycle signal resetting said clock enable means to interrupt said clock.

Claim 36

The card of claim 29 wherein said memory means comprises a counter responsive to said clock means for providing addresses and a memory circuit responsive to said addresses for supplying said first stored code to said comparator means, said clock means continuing to drive said counter if said received signal has been successfully compared to said first stored code and for interrupting said counter if said first stored code signal is not successfully compared to said received signal.

Claim 37

The card of claim 34 wherein said counter has a plurality of outputs and said memory means further comprises a decoder circuit for decoding selected outputs of said counter for enabling said transmit means to transmit said second stored code only during a transmit mode, said transmit mode only occurring after the first stored code has been compared to the received signal.

Claim 38

The card of claim 35 wherein said memory means comprises an end of cycle decoder connected to selected outputs from said counter for providing an end of cycle signal after said second stored code has been supplied by said memory means to said transmit means, said end of cycle signal resetting said clock means to interrupt said clock means.

Claim 39

The card of claim 29 wherein said memory means comprises a counter-driven by said clock means and having a plurality of outputs, and a decoder circuit for decoding selected outputs of said counter for enabling said transmit means to transmit said second stored code only during a transmit mode, said transmit mode only occurring after the first stored code has been compared to the received signal.

Claim 40

The card of claim 37 wherein said memory means comprises an end of cycle decoder connected to selected outputs from said counter for providing an end of cycle signal after said second stored code has been supplied by said memory means to said transmit means, said end of cycle signal resetting said clock means to interrupt said clock means.