US4352210A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Linear mixer with reduced spurious responses
Assignee: General Electric Co
•
Filing: 1980-09-12
•
Granted: 1982-09-28
•
Expires: 2000-09-12
Abstract
Abstract A linear mixer, having essentially no spurious responses below the fifth harmonic of a local oscillator frequency, utilizes a balanced demodulator summation network having first and second inputs each receiving an RF input signal via an associated one of a pair of switches operated at the local oscillator frequency. The local oscillator waveform is selected to eliminate the third harmonic thereof, whereby a baseband signal output of the summation network is a signal having essentially zero magnitude responses at at least the second, third, fourth and sixth harmonics of the oscillator frequency. Digital circuitry to provide the required oscillator waveform is disclosed.
Inventors
- 👤 Charles M. Puckette
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:49
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/30; H03; H03D; H03D7/00; H03D7/12; H03D7/125; H03B; H03B1/00; H03B1/04; H03D2200/00; H03D2200/0041; H03D2200/0066; H03D2200/0078
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
157 words
A reduced-spurious-response mixer circuit comprising: an input terminal receiving an input signal; an output terminal; a balanced differential summing network having an inverting input, a non-inverting input and an output connected to said output terminal; first and second switch means for selectively coupling said input signal from said input terminal respectively to said summing network inverting and non-inverting inputs responsive respectively to first and second local oscillator signals; and means for providing said first and second local oscillator signals as digital waveforms each having first binary values for one-third of a time interval equal to the reciprocal of the local oscillator frequency, and having a second binary value at all other times, said first and second signals being offset from one another by a time interval equal to one-half the local-oscillator time interval, to cause the third harmonic of said local oscillator frequency to have an essentially zero magnitude in a waveform resulting at said output terminal.
Claim 2
Dependent Claim
157 words
A reduced-spurious-response mixer circuit comprising: an input terminal receiving an input signal; an output terminal; a balanced differential summing network having an inverting input, a non-inverting input and an output connected to said output terminal; first and second switch means for selectively coupling said input signal from said input terminal respectively to said summing network inverting and non-inverting inputs responsive respectively to first and second local oscillator signals; and means for providing said first and second local oscillator signals as digital waveforms each having first binary values for one-third of a time interval equal to the reciprocal of the local oscillator frequency, and having a second binary value at all other times, said first and second signals being offset from one another by a time interval equal to one-half the local-oscillator time interval, to cause the third harmonic of said local oscillator frequency to have an essentially zero magnitude in a waveform resulting at said output terminal.
Claim 3
Dependent Claim
25 words
The circuit of claim 1, wherein the input and local oscillator frequencies are essentially identical, and said output terminal waveform is a baseband signal output.
Claim 4
Dependent Claim
25 words
The circuit of claim 2, wherein said output terminal waveform also has an essentially zero magnitude response at even harmonics of said local oscillator frequency.
Claim 5
Dependent Claim
97 words
The circuit of claim 1, wherein said first and second switch means each include a resistance element connected between said input terminal and an associated one of said summing network inverting and non-inverting inputs; and first and second switching devices each having a controlled-resistance circuit connected between ground potential and an associated one of said summing network inverting and non-inverting inputs, each switching device resistance circuit switching from a first to a second magnitude responsive respectively to an associated one of said first and second local oscillator signals being respectively at said first and second binary values.
Claim 6
Dependent Claim
83 words
The circuit of claim 4, wherein each device is a field-effect transistor having a gate electrode, a source electrode and a drain electrode; one of the source and drain electrodes of each device being connected to ground potential and the remaining one of the source and drain electrodes of each field-effect transistor being connected to the associated one of said summing network inverting and non-inverting inputs; the gate electrode of each said transistor receiving one of said first and second local oscillator signals.
Claim 7
Dependent Claim
53 words
The circuit of claim 5, wherein each of said first and second switch means further comprises a logic inverter having an output connected to the gate electrode of the associated one of said first and second switching devices and an input receiving an associated one of said first and second local oscillator signals.
Claim 8
Dependent Claim
14 words
The circuit of claim 1, wherein said summing network includes a differential video amplifier.
Claim 9
Dependent Claim
25 words
The circuit of claim 1, further comprising a resistance element connected at said input terminal for providing a characteristic terminating impedance to said input signal.
Claim 10
Dependent Claim
165 words
The circuit of claim 1, wherein said oscillator signal providing means comprises: oscillator means for providing a logic waveform having a frequency equal to six times the local oscillator frequency; a synchronous counter having a clock input receiving the output waveform of said oscillator means, at least three synchronous binary-counting stages each having an output, and a load input for resetting the logic level at each of said at least three counting stage outputs to said second binary value; a NAND gate having a first input connected to the first counting state output, a second input connected to the third counting stage output, and an output connected to said load input; said first local oscillator signal being provided at said counter second counting stage output; and a type-D flip-flop logic element having a clock input receiving the output waveform of said oscillator means, a data input connected to the third counting stage output of said counter, and an output providing said second local oscillator signal.
References Cited (Backward Citations)
US3525941A
Cited
US3628154A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-09-27 | 1986-03-29 | 1986-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-09-27 | 1990-03-29 | 1990-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-09-27 | 1994-03-29 | 1994-09-28 | $7700.00 | Window Closed / Lapsed |