Self-limiting video signal peaking circuit

Claim 2

A video signal peaking network exhibiting a given amplitude versus frequency response including a frequency at which maximum signal peaking is produced, comprising: a source of video signals to be peaked including periodic and aperiodic amplitude transitions of varying magnitudes occupying a given range of transition magnitudes; a signal delay network with an input coupled to said source of video signals and an output, said delay network being terminated to operate in a reflective mode and exhibiting a signal delay for determining said maximum signal peaking frequency; a differential amplifier with a first input coupled to said delay network input and a second input coupled to said delay network output, for developing a peaking component at an output; a combining network for combining delayed signals from said delay network output with said peaking component from said differential amplifier output, for providing a peaked video signal; and wherein said differential amplifier (1) exhibits a linear response for aperiodic transitions of magnitudes throughout said range, and (2) exhibits a non-linear response for periodic transitions recurring at said maximum peaking frequency and having a magnitude greater than half the maximum transition magnitude of said range, such that said differential amplifier develops an amplitude limited peaking component at said amplifier output in response to said periodic transitions of said maximum peaking frequency.

Claim 3

A network according to claim 1, wherein said signal delay provided by said delay network is such that delayed periodic signals developed at said second differential amplifier input are antiphased in relation to delayed and reflected periodic signals developed at said first differential amplifier input, when said periodic video signals exhibit said maximum peaking frequency.

Claim 4

A network according to claim 2, wherein said differential amplifier comprises first and second transistors with input electrodes, interconnected common electrodes, and output electrodes; said input of said first transistor being coupled to said input of said delay network, said input of said second transistor being coupled to said output of said delay network; and said combining network comprises a third transistor with an input electrode coupled to said output of said delay network, a common electrode, and an output electrode coupled to said output electrode of said second transistor and to a signal combining load impedance.

Claim 5

A network according to claim 3, wherein said input, output and common electrodes of said first, second and third transistors correspond to base, collector and emitter electrodes.

Claim 6

A network according to claim 3 included in a system for processing a video signal containing image representative luminance and chrominance components disposed within a frequency spectrum of said video signal in frequency interleaved relation, said system including a comb filter for providing at a first output a combed luminance signal with amplitude peaks at integral multiples of an image line scanning frequency and amplitude nulls at odd multiples of one-half said line frequency, and for providing at a second output a signal with amplitude peaks at odd multiples of one-half said line frequency and amplitude nulls at integral multiples of said line frequency, and wherein signals provided at said second output include signal frequencies representative of luminance vertical image detail information absent from said combed luminance signal at said first output; means coupled to said second comb filter output for selectively passing said signal frequencies corresponding to vertical detail signal information, to the exclusion of signals occupying the band of chrominance signal frequencies; and means for processing said selectively passed vertical detail signals; and wherein said video signals to be peaked by said peaking network correspond to said luminance component; and said processed vertical detail signals are coupled to said output electrode of said third transistor for combining with peaked signals developed at said output of said third transistor.

Claim 7

A video signal peaking network exhibiting a given amplitude versus frequency response including a frequency at which maximum signal peaking is produced, comprising: a source of video signals to be peaked including periodic and aperiodic amplitude transitions of varying magnitudes occupying a given range of transition magnitudes; a signal delay network with an input coupled to said source of video signals and an output, said delay network being terminated to operate in a reflective mode and exhibiting a signal delay for determining said maximum signal peaking frequency; a differential amplifier comprising first and second transistors, with input electrodes, interconnected common electrodes, and output electrodes; said input of said first transistor being coupled to said input of said delay network, and said input of said second transistor being coupled to said output of said delay network; and a signal combining network comprising a third transistor with an input electrode coupled to said output of said delay network, a common electrode, and an output electrode coupled to said output electrode of said second transistor and to a signal combining load impedance.

Claim 8

A video signal peaking network exhibiting a given amplitude versus frequency response including a frequency at which maximum signal peaking is produced, comprising: a source of video signals to be peaked including periodic and aperiodic amplitude transitions of varying magnitudes occupying a given range of transition magnitudes; a signal delay network with an input coupled to said source of video signals and an output, said delay network being terminated to operate in a reflective mode and exhibiting a signal delay for determining said maximum signal peaking frequency; a differential amplifier comprising first and second transistors, with input electrodes, interconnected common electrodes, and output electrodes; said input of said first transistor being coupled to said input of said delay network, and said input of said second transistor being coupled to said output of said delay network; and a signal combining network comprising a third transistor with an input electrode coupled to said output of said delay network, a common electrode, and an output electrode coupled to said output electrode of said second transistor and to a signal combining load impedance.

Claim 9

A network according to claim 6 included in a system for processing a video signal containing image representative luminance and chrominance components disposed within a frequency spectrum of said video signal in frequency interleaved relation, said system including a comb filter for providing at a first output a combed luminance signal with amplitude peaks at integral multiples of an image line scanning frequency and amplitude nulls at odd multiples of one-half said line frequency, and for providing at a second output a signal with amplitude peaks at odd multiples of one-half said line frequency and amplitude nulls at integral multiples of said line frequency, and wherein signals provided at said second output include signal frequencies representative of luminance vertical image detail information absent from said combed luminance signal at said first output; means coupled to said second comb filter output for selectively passing said signal frequencies corresponding to vertical detail signal information, to the exclusion of signals occupying the band of chrominance signal frequencies; and means for processing said selectively passed vertical detail signals; and wherein said video signals to be peaked by said peaking network correspond to said luminance component; and said processed vertical detail signals are coupled to said output electrode of said third transistor for combining with peaked signals developed at said output of said third transistor.