Multiple console control system

Claim 2

A control system for selectively controlling a device, said device comprising a control common line and at least one switch line, said control system comprising: a momentary action switch coupling said control common line to said switch line; a memory element including an input coupled to said switch line and including an output, said memory element comprising a control input selectively operable to load information from said switch line to store information previously loaded; means for selectively coupling said output of said memory element to said input; and control means for causing said memory element to load information from said switch line while causing said means for selectively coupling to decouple said output of said memory element from the input thereof whenever the information at said input and output of said memory element are different, and for causing said memory element to store while causing said means for selectively coupling to couple said output of said memory element to said input thereof whenever the information at said input and output of said memory element are the same.

Claim 3

A control system according to claim 1 wherein said means for selectively coupling comprises a gated amplifier having an input coupled to the output of said memory element and an output coupled to the input of said memory element and to said switch line and having a control input for causing coupling and decoupling said amplifier from the output of said memory element to the input thereof.

Claim 4

A control system according to either of claims 1 or 2 wherein said control means comprises a logic circuit having a first input coupled to the input of said memory element, a second input coupled to the output of said memory element, and an output coupled to the control input said memory element for causing it to load or store, said output of said logic circuit also being coupled to the control input of said means for selectively coupling for controlling the coupling and decoupling of the output of said memory element to the input thereof.

Claim 5

A control system according to claim 3 further including a delay element coupled between the output of said logic circuit and said memory element.

Claim 6

A control system according to either of claims 1 or 2 further comprising an indicator coupled to said switch line for indicating the status of said memory element.

Claim 7

A control system according to claim 3 further comprising an indicator coupled to said switch line for indicating the status of said memory element.

Claim 8

A control system according to claim 4 further comprising an indicator coupled to said switch line for indicating the status of said memory element.

Claim 9

A control system according to either of claims 1 or 2 further including plural switches and plural switch lines, one switch line being associated with each such switch, and plural memory elements, one such memory element associated with each switch.

Claim 10

A control system according to claim 3 wherein said logic circuit comprises at least one exclusive OR gate having a first input coupled to the input of said memory element and a second input coupled to the output of said memory element.

Claim 11

A control system according to claim 9 further including a delay element coupled between the output of said logic circuit and said memory element.

Claim 12

A control system according to claim 9 further comprising an indicator coupled to said switch line for indicating the status of said memory element.

Claim 13

A control system according to claim 10 further comprising an indicator coupled to said switch line for indicating the status of said memory element.

Claim 14

A control system according to claim 8 wherein said control means comprises a logic circuit having a first set of inputs coupled to respective inputs of each of said memory elements, a second set of inputs coupled to respective outputs of each of said memory elements, and an output coupled to the control input of all of said memory elements for causing said elements to load or store, said output of said logic circuit also being coupled to the control input of said means for selectively coupling for controlling the coupling and decoupling of the output of each of said memory elements to the inputs thereof.

Claim 15

A control system according to claim 13 wherein said logic circuit comprises: an exclusive OR gate corresponding to each of said memory elements, one input of each of said exclusive OR gates being coupled to the input of its corresponding memory element and a second input of each of said exclusive OR gates being coupled to the output of its corresponding memory element; and an OR gate having an input coupled to the output of each of said exclusive OR gates, the output of said OR gate serving as the output of said logic circuit.

Claim 16

A control device for selectively controlling a system on a device circuit board, said device comprising a device common line and at least one device switch line, said control system comprising: a back plane circuit board having a back plane common line for coupling to said device control common line and a back plane switch line for coupling to said device switch line when said back plane circuit board and said device circuit board are jointed; a first switch system having a switch system common line for coupling to said back plane common line, a switch system switch line for coupling to said back plane switch line, and at least one momentary switch coupling said switch system common line to said switch system switch line; and a control circuit board including a memory element having an input, an output, and a control input for controlling whether the memory element loads data from its input or maintains previously loaded data in a stored condition, means for selectively coupling the output of said memory element to the input thereof, control means coupled to the control input of said memory element and to said means for selectively coupling, and means for coupling the input of said memory element to said back plane switch line when said control circuit board is coupled to said back plane circuit board.

Claim 17

A control device for selectively controlling a system on a device circuit board, said device comprising a device common line and at least one device switch line, said control system comprising: a back plane circuit board having a back plane common line for coupling to said device control common line and a back plane switch line for coupling to said device switch line when said back plane circuit board and said device circuit board are jointed; a first switch system having a switch system common line for coupling to said back plane common line, a switch system switch line for coupling to said back plane switch line, and at least one momentary switch coupling said switch system common line to said switch system switch line; and a control circuit board including a memory element having an input, an output, and a control input for controlling whether the memory element loads data from its input or maintains previously loaded data in a stored condition, means for selectively coupling the output of said memory element to the input thereof, control means coupled to the control input of said memory element and to said means for selectively coupling, and means for coupling the input of said memory element to said back plane switch line when said control circuit board is coupled to said back plane circuit board.

Claim 18

A control system according to claim 15 wherein said means for selectively coupling is a gated amplifier.

Claim 19

A control system according to either of claims 15 or 16 wherein said control means is a logic circuit having a first input coupled to the input of said memory element and a second input coupled to the output of said memory element.

Claim 20

A control system according to either of claims 15 or 16 further including a delay element coupling said control means to said means for selectively coupling.

Claim 21

A control system according to either of claims 15 or 16 further including an indicator coupled to said switch line for indicating the status of said memory element.

Claim 22

A control system according to claim 17 further including an indicator coupled to said switch line for indicating the status of said memory element.

Claim 23

A control system according to claim 18 further including an indicator coupled to said switch line for indicating the status of said memory element.

Claim 24

A control system according to claim 17 wherein said logic circuit includes at least one exclusive OR gate having a first input coupled to the input of said memory element and having a second input coupled to the output of said memory element.

Claim 25

A control system for selectively controlling a control device on a device circuit board, said device comprising a device control common line and at least one device switch line comprising, said control system comprising: a back plane circuit board having a back plane common line for coupling to said device control common line and a back plane switch line for coupling to said device switch line when said back plane circuit board and said device circuit board are joined; a first switch system having a switch system common line for coupling to said back plane common line, a switch system switch line for coupling to said back plane switch line, and at least one momentary switch coupling said switch system common line to said switch system switch line; and a control circuit board for coupling in parallel to said back plane common and back plane switch lines including means for sensing the actuation of said one momentary switch and providing, in response to said switch actuation, a signal on said back plane switch line for controlling said device.

Claim 26

A control system for selectively controlling a control device on a device circuit board, said device comprising a device control common line and at least one device switch line comprising, said control system comprising: a back plane circuit board having a back plane common line for coupling to said device control common line and a back plane switch line for coupling to said device switch line when said back plane circuit board and said device circuit board are joined; a first switch system having a switch system common line for coupling to said back plane common line, a switch system switch line for coupling to said back plane switch line, and at least one momentary switch coupling said switch system common line to said switch system switch line; and a control circuit board for coupling in parallel to said back plane common and back plane switch lines including means for sensing the actuation of said one momentary switch and providing, in response to said switch actuation, a signal on said back plane switch line for controlling said device.

Claim 27

A control system according to claim 23 wherein said switch further includes at least one indicator coupled to said switch systems switch line for indicating the status of the signal in said switch line.

Claim 28

A control system according to either of claims 23 or 24 wherein said means for sensing comprises: a memory element having an input coupled to said back plane switch line; means for selectively coupling the output of said memory element to both the input thereof and to said back plane switch line; and logic circuit means for sensing whether there is a difference between the information at the input and output of said memory element and for causing said memory element to load new information when there is such a difference and to store previously loaded information when there is no difference, said logic circuit means further for causing said means for selectively coupling to couple when there is no difference and to decouple when there is a difference.

Claim 29

A control system according to claim 25 wherein said logic circuit means includes an exclusive OR gate coupled to the input and output of each memory element and an OR gate having an input coupled to the output of each of said exclusive OR gates, the output of said OR gate being the output of said logic circuit means.

Claim 30

An arrangement for selectively controlling a device, said device comprising a device control common line and at least one device switch line, said arrangement comprising: a coupling circuit, said coupling circuit comprising a control common line for coupling to said device common line and a switch line for coupling to said device switch line in response to said coupling circuit and said device being coupled together; a first switch system having a switch system common line for coupling to said coupling circuit common line, a switch system switch line for coupling to said coupling circuit switch line, at at least one momentary switch coupling said first switch system common line to said switch system switch line; and a memory element having an input, an output, and a control input for controlling whether the memory element loads new information or previously loaded information, means for selectively coupling the output of said memory element to the input thereof, control means coupled to the control input of said memory element and to said means for seldctively coupling, and means for coupling the input of said memory element to said coupling circuit switch line in response to said memory element being coupled to said coupling circuit.

Claim 31

An arrangement for selectively controlling a device, said device comprising a device control common line and at least one device switch line, said arrangement comprising: a coupling circuit, said coupling circuit comprising a control common line for coupling to said device common line and a switch line for coupling to said device switch line in response to said coupling circuit and said device being coupled together; a first switch system having a switch system common line for coupling to said coupling circuit common line, a switch system switch line for coupling to said coupling circuit switch line, at at least one momentary switch coupling said first switch system common line to said switch system switch line; and a memory element having an input, an output, and a control input for controlling whether the memory element loads new information or previously loaded information, means for selectively coupling the output of said memory element to the input thereof, control means coupled to the control input of said memory element and to said means for seldctively coupling, and means for coupling the input of said memory element to said coupling circuit switch line in response to said memory element being coupled to said coupling circuit.