US4348602A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current comparator circuit with deadband
Assignee: National Semiconductor Corp
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Filing: 1980-09-15
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Granted: 1982-09-07
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Expires: 2000-09-15
Abstract
Abstract A pair of differentially related currents are caused to flow in a pair of current modes. A symmetrical current mirror is coupled to the nodes and level shifting means coupled from each node to the current mirror common terminal. A pair of output transistors have their bases directly coupled to the nodes and their emitters cross coupled to the same nodes so that when the nodes are driven to a one V BE differential, output collector current will flow. The output transistors have their collectors commonly coupled to the circuit output. Deadband control means are connected to the current mirror common terminal so that no output current will flow until the deadband differential is exceeded.
Inventors
- 👤 Don R. Sauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:57
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/30; G; G01; G01R; G01R19/00; G01R19/0038
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
140 words
A current comparator circuit with controlled deadband wherein the difference between differential currents is sensed and an output provided when said difference exceeds a predetermined value, said circuit comprising: a pair of circuit nodes; means for passing differential currents through said nodes; current mirror means coupled to said nodes, said current mirror means having a common control terminal, a pair of current reflecting terminals coupled to said nodes, and deadband control means coupled to said common control terminal; level shifting means coupled between said common control terminal and ech of said nodes; and a pair of output transistors having their collectors commonly coupled to provide said output, their bases coupled to said nodes and their emitters cross coupled to said nodes whereby said output only occurs when said differential currents exceed a difference limit determined by said deadband control means.
Claim 2
Dependent Claim
140 words
A current comparator circuit with controlled deadband wherein the difference between differential currents is sensed and an output provided when said difference exceeds a predetermined value, said circuit comprising: a pair of circuit nodes; means for passing differential currents through said nodes; current mirror means coupled to said nodes, said current mirror means having a common control terminal, a pair of current reflecting terminals coupled to said nodes, and deadband control means coupled to said common control terminal; level shifting means coupled between said common control terminal and ech of said nodes; and a pair of output transistors having their collectors commonly coupled to provide said output, their bases coupled to said nodes and their emitters cross coupled to said nodes whereby said output only occurs when said differential currents exceed a difference limit determined by said deadband control means.
Claim 3
Dependent Claim
14 words
The circuit of claim 1 wherein said level shifting means are diode connected transistors.
Claim 4
Dependent Claim
22 words
The circuit of claim 2 wherein said current mirror means, said level shifting means and said output transistors are all NPN transistors.
Claim 5
Dependent Claim
31 words
The circuit of claim 3 wherein said deadband control means comprises a diode connected NPN transistor that is ratioed in size with respect to the size of said current mirror transistors.
Claim 6
Dependent Claim
22 words
The circuit of claim 3 wherein said deadband control means is an NPN transistor with separate biasing means to control said deadband.
Claim 7
Dependent Claim
22 words
The circuit of claim 2 wherein said current mirror means, said level shifting means and said output transistors are all PNP transistors.
Claim 8
Dependent Claim
32 words
The circuit of claim 6 wherein said current mirror means comprise plural collector lateral transistors with one collector returned directly to its base and another collector returned to one of said nodes.
Claim 9
Dependent Claim
15 words
The circuit of claim 7 wherein said plural collectors are ratioed to control said deadband.
References Cited (Backward Citations)
US4069460A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-09-06 | 1986-03-08 | 1986-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-09-06 | 1990-03-08 | 1990-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-09-06 | 1994-03-08 | 1994-09-07 | $7700.00 | Window Closed / Lapsed |