US4348585A
Expired / Lapsed
US
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Frequency/speed controller
Assignee: Caterpillar Inc
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Filing: 1979-04-02
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Granted: 1982-09-07
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Expires: 1999-04-02
Abstract
Abstract A frequency/speed controller is provided for controlling the frequency or speed of a device by comparing the frequency of the device to a known reference frequency and matching the device frequency with the reference frequency. The controller uses an up/down counter whose count at any given time is the digital quantized form of ##EQU1## where f 1 and f 2 are the frequencies to be matched.
Inventors
- 👤 John P. Hoffman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:36
CPC Classifications
G; G01; G01P; G01P3/00; G01P3/42; G01P3/56; G01P3/60; H; H02; H02P; H02P23/00; H02P23/22; Y; Y10; Y10S; Y10S388/00; Y10S388/90; Y10S388/907; Y10S388/912
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
221 words
An integrating frequency-difference counter (18) comprising: an up/down counter (24) having an up/down input (26), a clock input (28) and an output (30), said counter (24) being free to count in response to receiving a clock signal at the clock input (28), free to count up in response to receiving an up count signal at the up/down input (26), and free to count down in response to receiving a down count signal at the up/down input (26); signal generating means (64,66) for generating first, second, third and fourth outputs (68,70,72, 74), said outputs (68,70,72,74) being generated at a preselected frequency in a preselected sequential order; first means (94,96,98,100) for receiving a first reference frequency signal of frequency f 1 , combining the first frequency signal with the first output (68) in a preselected manner, and producing the clock signal; second means (94',96',98',100') for receiving a second controlled frequency signal of frequency f 2 , combining the second frequency signal with the third output (72) in a preselected manner, and producing the clock signal; third means (76,78) for receiving the second output (70) and producing the down count signal; and fourth means (78,80) for receiving the fourth output (74) and producing the up count signal, the output (30) of the counter (24) at any time being the digital guantized form of ##EQU4##
Claim 2
Dependent Claim
221 words
An integrating frequency-difference counter (18) comprising: an up/down counter (24) having an up/down input (26), a clock input (28) and an output (30), said counter (24) being free to count in response to receiving a clock signal at the clock input (28), free to count up in response to receiving an up count signal at the up/down input (26), and free to count down in response to receiving a down count signal at the up/down input (26); signal generating means (64,66) for generating first, second, third and fourth outputs (68,70,72, 74), said outputs (68,70,72,74) being generated at a preselected frequency in a preselected sequential order; first means (94,96,98,100) for receiving a first reference frequency signal of frequency f 1 , combining the first frequency signal with the first output (68) in a preselected manner, and producing the clock signal; second means (94',96',98',100') for receiving a second controlled frequency signal of frequency f 2 , combining the second frequency signal with the third output (72) in a preselected manner, and producing the clock signal; third means (76,78) for receiving the second output (70) and producing the down count signal; and fourth means (78,80) for receiving the fourth output (74) and producing the up count signal, the output (30) of the counter (24) at any time being the digital guantized form of ##EQU4##
Claim 3
Dependent Claim
34 words
A counter (18), as set forth in claim 1, wherein the signal generating means (64,66) sequentially generates the first output (68), the third output (72), the second output (70), and the fourth output (74).
Claim 4
Dependent Claim
33 words
A counter (18), as set forth in claim 1, wherein the signal generating means (64,66) sequentially operates at a rate at least four times as fast as the first and second frequency signals.
Claim 5
Dependent Claim
79 words
A counter (18), as set forth in claim 1 wherein the first means (94,96,98,100) includes a NAND gate (94) having an output coupled to the clock input (28) of the up/down counter (24), a first input coupled to the first output (68) of the signal generating means (64,66), and a second input; and a flip-flop (96) having an input for receiving the first reference frequency signal and an output connected to the second input of the NAND gate (94).
Claim 6
Dependent Claim
34 words
A counter (18), as set forth in claim 4, including a monostable (100) having an output connected to the input of the flip-flop (96) and an input for receiving the first reference frequency signal.
Claim 7
Dependent Claim
39 words
A counter (18), as set forth in claim 4, including a monostable (100) having an input connected to the output of the NAND gate (94) and an output coupled to the clock input (28) of the up/down counter (24).
Claim 8
Dependent Claim
31 words
A counter (18), as set forth in claim 6, wherein the flip-flop (96) has a reset input and wherein the output of the monostable (100) is connected to the reset input.
Claim 9
Dependent Claim
48 words
A counter (18), as set forth in claim 1, including an OR gate (102) having an output connected to the clock input (28) of the up/down counter (24), a first input connected to the first means (94,96,98, 100) and a second input connected to the second means (94',96',98',100').
Claim 10
Dependent Claim
63 words
A counter (18), as set forth in claim 1, wherein the third means (78,80) includes a flip-flop (78) having an output coupled to the up/down input (26) of the up/down counter (24), a set input coupled to the fourth output (74) of the signal generating means (64,66), and a reset input coupled to the second output (70) of the signal generating means (64,66).
Claim 11
Dependent Claim
25 words
A counter (18), as set forth in claim 1, including means (82,84,86,88,90,92) for preventing the up/down counter (24) from counting up or down through zero.
Claim 12
Independent Claim
135 words
An apparatus for controlling the speed of a device, comprising: means for supplying a first frequency proportional to a reference speed signal; means for supplying a second frequency proportional to an actual speed signal; an integrating frequency difference counter having first and second frequency inputs adapted to receive said first and second frequencies and a digital count output; and means for instantaneously doubling said digital count output in response to said first frequency input receiving at least three consecutive frequency pulses during a period in which said second frequency input is free from receiving any frequency pulses, and for instantaneously halving said digital count output in response to said second frequency input receiving at least three consecutive frequency pulses during a period in which said first frequency input is free from receiving any frequency pulses.
Claim 13
Independent Claim
135 words
An apparatus for controlling the speed of a device, comprising: means for supplying a first frequency proportional to a reference speed signal; means for supplying a second frequency proportional to an actual speed signal; an integrating frequency difference counter having first and second frequency inputs adapted to receive said first and second frequencies and a digital count output; and means for instantaneously doubling said digital count output in response to said first frequency input receiving at least three consecutive frequency pulses during a period in which said second frequency input is free from receiving any frequency pulses, and for instantaneously halving said digital count output in response to said second frequency input receiving at least three consecutive frequency pulses during a period in which said first frequency input is free from receiving any frequency pulses.
Claim 14
Dependent Claim
21 words
An apparatus, as set forth in claim 11, wherein said means for instantaneously doubling and for instantaneously halving includes a microprocessor.
Claim 15
Dependent Claim
21 words
An apparatus, as set forth in claim 11, wherein said doubling said digital count output includes left shifting said digital count.
Claim 16
Dependent Claim
21 words
An apparatus, as set forth in claim 11, wherein said halving said digital count output includes right shifting said digital count.
References Cited (Backward Citations)
US3110853A
Cited
US3548169A
Cited
US3543116A
Cited
US3724720A
Cited
US3974428A
Cited
US3989931A
Cited
US4130785A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-09-06 | 1986-03-08 | 1986-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-09-06 | 1990-03-08 | 1990-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-09-06 | 1994-03-08 | 1994-09-07 | $7700.00 | Window Closed / Lapsed |