US4346472A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for eliminating double bit errosion in a differential phase shift keying system
Assignee: HITACHI Ltd AND NIPPON TELEGRAPH & TELEPHONE PUBLIC Corp AND 1-6 UCHISAIWAICHO-1-CHOME CHIYODA-KU TOKYO JAPAN CORPS OF JAPAN
•
Filing: 1980-08-07
•
Granted: 1982-08-24
•
Expires: 2000-08-07
Abstract
Abstract A code converting circuit of simple construction composed of an exclusive OR circuit and a flip-flop circuit is provided on each of transmitting and receiving sides of a digital data transmission system according to a differential phase shift keying system, to convert two consecutive errors on adjacent bits peculiar to the differential phase shift keying system into only an error on a single bit. As a result, it is not required to employ a code having an excellent error-correcting capacity in the digital data transmission system, and thus a high transmission efficiency is attained by the use of a code which is relatively deficient in error correcting capacity.
Inventors
- 👤 Seiei Ohkoshi
- 👤 Isao Ishikawa
- 👤 Teiji Okamoto
- 👤 Nobuo Tsukamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:53
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2275; H04L27/20; H04L27/2032; H04L27/2035
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
239 words
An information coding method usable in a digital data transmission system for transmitting digital data in frames containing n bits with each frame including error correcting code bits and information bits modulated by differential phase shift keying, comprising the steps of: forming for each frame of digital data an individual code for transmission in such a manner that a first transmitted bit of said code for transmission is made equal to a first bit of said error correcting code and an i-th transmitted bit (2≦i≦n) of said code for transmission is formed by a modulo 2 sum of the i-th and (i-1)th bits of said error correcting code; modulating said code for transmission by differential phase shift keying; transmitting said modulated code; demodulating said transmitted code by differential phase shift keying; forming a demodulated error correcting code from said demodulated transmitted code in such a manner that the first bit of said demodulated error correcting code is made equal to the first bit of said demodulated transmitted code and an i-th bit of said demodulated error correcting code is formed by a modulo 2 sum of an i-th bit of said demodulated transmitted code and an (1-1)th bit of said demodulated error correcting code; and performing an error correcting operation on said demodulated error correcting code to regenerate said information code, said error correcting operation being peculiar to said error correcting code having said code length of n bits.
Claim 2
Dependent Claim
239 words
An information coding method usable in a digital data transmission system for transmitting digital data in frames containing n bits with each frame including error correcting code bits and information bits modulated by differential phase shift keying, comprising the steps of: forming for each frame of digital data an individual code for transmission in such a manner that a first transmitted bit of said code for transmission is made equal to a first bit of said error correcting code and an i-th transmitted bit (2≦i≦n) of said code for transmission is formed by a modulo 2 sum of the i-th and (i-1)th bits of said error correcting code; modulating said code for transmission by differential phase shift keying; transmitting said modulated code; demodulating said transmitted code by differential phase shift keying; forming a demodulated error correcting code from said demodulated transmitted code in such a manner that the first bit of said demodulated error correcting code is made equal to the first bit of said demodulated transmitted code and an i-th bit of said demodulated error correcting code is formed by a modulo 2 sum of an i-th bit of said demodulated transmitted code and an (1-1)th bit of said demodulated error correcting code; and performing an error correcting operation on said demodulated error correcting code to regenerate said information code, said error correcting operation being peculiar to said error correcting code having said code length of n bits.
Claim 3
Dependent Claim
41 words
An information coding system according to claim 1, wherein said step of forming said code for transmission includes a step of forming an exclusive OR between a current input bit of said error correcting code and an immediately preceding input bit.
Claim 4
Dependent Claim
46 words
An information coding system according to claim 1, wherein said step of forming said demodulated error correcting code includes a step of forming an exclusive OR between a current output bit of said code for transmission having been been demodulated and an immediately preceding generated bit.
Claim 5
Dependent Claim
43 words
An information coding system according to claim 1, wherein each of said steps of forming said code for transmission and of forming said demodulated error correcting code is taken at an interval of one frame equal to said code length of n bits.
Claim 6
Dependent Claim
268 words
In a system for transmitting digital data in frames containing n bits with each frame including error correcting code bits and information bits modulated by, including an error correcting code generating circuit for generating an error correcting code from information codes, a differential phase shift keying circuit for modulating said error correcting code for transmission, a demodulating circuit for demodulating said modulated error correcting code, and an error correcting code decoding circuit for decoding said error correcting code, the improvement comprising: first means for code conversion provided between said error correcting code generating circuit and said different phase shift keying circuit, including a first exclusive OR circuit and a first flip-flop circuit, to convert each frame of said error correcting code individually in such a manner that the first bit of a converted code is made equal to the first bit of said error correcting code and an i-th bit (2≦i≦n) of said converted code is formed by a modula 2 sum of (i-1)th and i-th bits of said error correcting code; and second means for code conversion provided between said demodulating circuit and said error correcting code decoding circuit, including a second exclusive OR circuit and a second flip-flop circuit, to conduct code conversion at an interval of one frame in such a manner that the first bit of a converted code is made equal to the first bit of a demodulated transmitted code and an i-th bit (2≦i≦n) of said converted code is formed by a modula 2 sum of an (i-1)th bit of said demodulated transmitted code and an (i-1)th bit of said converted code.
Claim 7
Dependent Claim
268 words
In a system for transmitting digital data in frames containing n bits with each frame including error correcting code bits and information bits modulated by, including an error correcting code generating circuit for generating an error correcting code from information codes, a differential phase shift keying circuit for modulating said error correcting code for transmission, a demodulating circuit for demodulating said modulated error correcting code, and an error correcting code decoding circuit for decoding said error correcting code, the improvement comprising: first means for code conversion provided between said error correcting code generating circuit and said different phase shift keying circuit, including a first exclusive OR circuit and a first flip-flop circuit, to convert each frame of said error correcting code individually in such a manner that the first bit of a converted code is made equal to the first bit of said error correcting code and an i-th bit (2≦i≦n) of said converted code is formed by a modula 2 sum of (i-1)th and i-th bits of said error correcting code; and second means for code conversion provided between said demodulating circuit and said error correcting code decoding circuit, including a second exclusive OR circuit and a second flip-flop circuit, to conduct code conversion at an interval of one frame in such a manner that the first bit of a converted code is made equal to the first bit of a demodulated transmitted code and an i-th bit (2≦i≦n) of said converted code is formed by a modula 2 sum of an (i-1)th bit of said demodulated transmitted code and an (i-1)th bit of said converted code.
Claim 8
Dependent Claim
110 words
An apparatus for coding information according to claim 5, wherein one input of said first exclusive OR circuit is connected to the output of said error correcting code generating circuit and an output terminal of said first exclusive OR circuit is connected to the input of said differential phase shift keying circuit, and wherein input and output terminals of said first flip-flop circuit are connected to the output of said error correcting code generating circuit and the other input of said first exclusive OR circuit, respectively, and reset and clock input terminals of said first flip-flop circuit are connected to receive a frame synchronizing signal and a clock signal, respectively.
Claim 9
Independent Claim
101 words
An apparatus for coding information according to claims 5 or 6, wherein one input of said second exlusive OR circuit is connected to the output of said demodulating circuit and an output of said second exclusive OR circuit is connected to the input of said error correcting code decoding circuit, and wherein input and output terminals of said second flip-flop circuit are connected to the output and the other input of said second exclusive OR circuit, respectively, and reset and clock input terminals of said second flip-flop circuit are connected to receive a frame synchronizing signal and a clock signal, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-23 | 1986-02-22 | 1986-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-23 | 1990-02-22 | 1990-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-23 | 1994-02-22 | 1994-08-24 | $7700.00 | Window Closed / Lapsed |