US4344133A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for synchronizing hardware and software
Assignee: Motorola Solutions Inc
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Filing: 1980-04-14
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Granted: 1982-08-10
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Expires: 2000-04-14
Abstract
Abstract A digital processor capable of responding to a sync instruction for high-speed synchronization of hardware and software is provided. The sync instruction places the procesor in a stopped state and lets the processor start up again only upon receipt of an interrupt. If the interrupt is disabled by being masked, the stopped state is simply cleared and the sequencing of instructions continues without vectoring to the interrupt service routine. However if the interrupt is not disabled, the processor will handle the interrupt just as it would if it were not in the stopped state. Upon return from the interrupt service routine, the stopped state is cleared and the sequencing of instructions continues. In this way, the sync instruction provides a mechanism for synchronizing software with hardware external to the processor without the delays associated with interrupts or busy-wait loops.
Inventors
- 👤 William C. Bruce, Jr.
- 👤 Fuad H. Musa
- 👤 Terry F. Ritter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30087; G06F9/30079
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
66 words
A method of providing high-speed synchronization between hardware and software in a digital processing system, comprising: performing a sync instruction to cause the digital processing system to assume a stopped state; waiting for an interrupt to occur; receiving an interrupt; and vectoring to an interrupt address to service the interrupt or fetching an op code which is next in sequence when the interrupt received is masked.
Claim 2
Independent Claim
66 words
A method of providing high-speed synchronization between hardware and software in a digital processing system, comprising: performing a sync instruction to cause the digital processing system to assume a stopped state; waiting for an interrupt to occur; receiving an interrupt; and vectoring to an interrupt address to service the interrupt or fetching an op code which is next in sequence when the interrupt received is masked.
Claim 3
Independent Claim
54 words
A method of synchronizing hardware and software in a digital system having a central processing unit and at least one peripheral device, comprising: stopping the central processing unit and waiting for an interrupt; and deciding whether to vector to an address for the interrupt or whether to fetch a next in sequence op code.
Claim 4
Independent Claim
54 words
A method of synchronizing hardware and software in a digital system having a central processing unit and at least one peripheral device, comprising: stopping the central processing unit and waiting for an interrupt; and deciding whether to vector to an address for the interrupt or whether to fetch a next in sequence op code.
Claim 5
Dependent Claim
20 words
The method of claim 2 wherein the next in sequence op code is fetched when the interrupt received is masked.
Claim 6
Independent Claim
67 words
A method of providing synchronization between hardware and software in a digital system having a central processing unit and at least one peripheral device, comprising: placing the central processing unit in a stopped state; waiting for an interrupt to occur; receiving the interrupt; clearing the stopped state of the central processing unit; and servicing the interrupt or continuing with sequence of instructions if the interrupt is disabled.
Claim 7
Independent Claim
67 words
A method of providing synchronization between hardware and software in a digital system having a central processing unit and at least one peripheral device, comprising: placing the central processing unit in a stopped state; waiting for an interrupt to occur; receiving the interrupt; clearing the stopped state of the central processing unit; and servicing the interrupt or continuing with sequence of instructions if the interrupt is disabled.
Claim 8
Independent Claim
109 words
A method of synchronizing hardware and software in a digital system having a central processing unit and at least one peripheral device, comprising: a. executing a sync instruction; b. waiting for an interrupt; c. receiving an interrupt and continuing with d, e, f, and g or continuing with the next instruction in a sequence of instructions thereby avoiding servicing the interrupt; d. getting data from an input port; e. storing the data and incrementing address; f. checking to determine whether all the data has been obtained from the input port; and g. repeating d, e, and f until all of the data has been obtained from the input port.
Claim 9
Independent Claim
109 words
A method of synchronizing hardware and software in a digital system having a central processing unit and at least one peripheral device, comprising: a. executing a sync instruction; b. waiting for an interrupt; c. receiving an interrupt and continuing with d, e, f, and g or continuing with the next instruction in a sequence of instructions thereby avoiding servicing the interrupt; d. getting data from an input port; e. storing the data and incrementing address; f. checking to determine whether all the data has been obtained from the input port; and g. repeating d, e, and f until all of the data has been obtained from the input port.
Claim 10
Independent Claim
53 words
A method of synchronizing hardware and software in a digital system having a central processing unit, comprising: setting a latch in response to a synchronizing instruction which places the central processing unit in a stopped state; waiting for an interrupt to occur; resetting the latch in response to the interrupt; and continuing processing.
Claim 11
Independent Claim
53 words
A method of synchronizing hardware and software in a digital system having a central processing unit, comprising: setting a latch in response to a synchronizing instruction which places the central processing unit in a stopped state; waiting for an interrupt to occur; resetting the latch in response to the interrupt; and continuing processing.
References Cited (Backward Citations)
US4003028A
Cited
US4004283A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-09 | 1986-02-08 | 1986-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-09 | 1990-02-08 | 1990-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-09 | 1994-02-08 | 1994-08-10 | $7700.00 | Window Closed / Lapsed |