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US4339674A Expired / Lapsed US ⏱️ 0.0 years remaining

Trigger circuit

Assignee: Toshiba Corp
•
Filing: 1980-09-12
•
Granted: 1982-07-13
•
Expires: 2000-09-12
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Abstract

Abstract A trigger circuit comprises first, second and third transistors whose emitters are connected in common to a constant current source, a current mirror having input and output terminals connected respectively to the collectors of the second and third transistors, a diode connected between the collector of the first transistor and the input terminal of the current mirror, and a switching transistor whose base and collector are connected respectively to the output terminal of the current mirror and the collector of the first transistor. The bases of the first and second transistors are connected in common to a first input terminal, while the base of the third transistor is connected to a second input terminal. A trigger signal is applied between the first and second input terminals. The diode and switching transistor are on and off respectively in one of two stable states of the trigger circuit, and are off and on respectively in the other. The threshold voltage levels of the circuit depend on the mirror ratio of the current mirror and the geometric dimensions of the first, second and third transistors.

Inventors

  • 👤 Masaru Hashimoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 11:56
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/2893; H03K3/2897

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 175 words
A trigger circuit comprising: first, second and third transistors of the same conductivity type each having a base, emitter and collector, said bases of said first and second transistors being connected in common, said emitters of said first, second and third transistors being connected in common, and said common-connected bases of said first and second transistors and said base of said third transistor being connected respectively to first and second input terminals between which a trigger signal is applied; a current source connected to said common-connected emitters of said first, second and third transistors; a current mirror having an input terminal and an output terminal connected respectively to said collectors of said second and third transistors; switching means connected between said input terminal of said current mirror and said collector of said first transistor; and means connected to said output terminal of said current mirror and said switching means for switching on and off said switching means in response to an output current of said current mirror and a collector current of said third transistor.
Claim 2
Dependent Claim 175 words
A trigger circuit comprising: first, second and third transistors of the same conductivity type each having a base, emitter and collector, said bases of said first and second transistors being connected in common, said emitters of said first, second and third transistors being connected in common, and said common-connected bases of said first and second transistors and said base of said third transistor being connected respectively to first and second input terminals between which a trigger signal is applied; a current source connected to said common-connected emitters of said first, second and third transistors; a current mirror having an input terminal and an output terminal connected respectively to said collectors of said second and third transistors; switching means connected between said input terminal of said current mirror and said collector of said first transistor; and means connected to said output terminal of said current mirror and said switching means for switching on and off said switching means in response to an output current of said current mirror and a collector current of said third transistor.
Claim 3
Dependent Claim 83 words
A trigger circuit according to claim 1, wherein said switching means includes a diode which is so connected as to allow a current to be supplied from said input terminal of said current mirror to said collector of said first transistor in an on state, and wherein said means for switching on and off said switching means includes a transistor having its base connected to said output terminal of said current mirror and its collector connected to said collector of said first transistor.
Claim 4
Dependent Claim 30 words
A trigger circuit according to claim 1, wherein said first, second and third transistors are of NPN-type, and said current mirror includes PNP-type transistors connected in a current mirror configuration.
Claim 5
Dependent Claim 24 words
A trigger circuit according to claim 2, wherein said transistor in said means for switching on and off said switching means is of PNP-type.

References Cited (Backward Citations)

US4013898A Cited
US3988595A Cited
US4210830A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1985-07-12 1986-01-11 1986-07-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1989-07-12 1990-01-11 1990-07-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1993-07-12 1994-01-11 1994-07-13 $7700.00 Window Closed / Lapsed

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