US4337777A
Expired / Lapsed
US
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Rate limited pacer
Assignee: Medtronic Inc
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Filing: 1980-12-24
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Granted: 1982-07-06
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Expires: 2000-12-24
Abstract
Abstract A pacer having an upper and lower rate limit system for preventing pacer malfunction from producing pacer output pulses above or below preset maximum and minimum rates.
Inventors
- 👤 Jerome T. Hartlaub
- 👤 Ray S. McDonald
- 👤 Lawrence C. Hudziak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:13
CPC Classifications
A; A61; A61N; A61N1/00; A61N1/18; A61N1/32; A61N1/36; A61N1/372; A61N1/37211; A61N1/362; A61N1/365
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
128 words
A rate limited pacer comprising: an oscillator for providing clock pulses at a clock rate; memory means for storing parameter data; pacer logic means for producing an input rate signal in response to stored parameter data and said clock pulses; and rate limit logic means responsive to said input rate signal and said clock pulses for producing an output rate signal equal to said input rate signal if said input rate signal is between an upper maximum rate limit and a lower dropout rate limit and for producing an output rate substantially equal to said maximum rate limit if said input rate signal exceeds said maximum rate limit and for producing an output rate at a minimum rate if said input rate is lower than said dropout rate.
Claim 2
Dependent Claim
128 words
A rate limited pacer comprising: an oscillator for providing clock pulses at a clock rate; memory means for storing parameter data; pacer logic means for producing an input rate signal in response to stored parameter data and said clock pulses; and rate limit logic means responsive to said input rate signal and said clock pulses for producing an output rate signal equal to said input rate signal if said input rate signal is between an upper maximum rate limit and a lower dropout rate limit and for producing an output rate substantially equal to said maximum rate limit if said input rate signal exceeds said maximum rate limit and for producing an output rate at a minimum rate if said input rate is lower than said dropout rate.
Claim 3
Dependent Claim
123 words
The pacer of claim 1 wherein said rate limit logic means includes: monitor means detecting input signal state transitions producing a counter reset signal in response to state transitions; counter means responsive to said clock pulses for producing a minimum rate interval signal, a maximum rate interval signal and a dropout rate interval signal; first means responsive to said maximum rate interval signal for gating said input signal to said output signal means when said input signal period exceeds said maximum rate interval; second means responsive to said dropout interval signal for preventing counter reset signals from resetting said counter; and third means responsive to said dropout interval signal for producing an output rate at a frequency corresponding to said minimum rate interval.
Claim 4
Dependent Claim
128 words
The pacer of claim 1 wherein said rate limit logic includes: monitor means detecting input signal state transitions producing a counter reset signal in response to state transitions; counter means responsive to said clock pulses for producing a first minimum rate interval signal, a second maximum rate interval signal and a third dropout rate interval signal; first logic means responsive to said maximum rate interval signal for gating said input signal to said output signal means when said input signal period exceeds said maximum rate interval; second logic means responsive to said dropout interval signal for preventing counter reset signals from resetting said counter; and third logic means responsive to said dropout interval signal for producing an output rate at a frequency corresponding to said minimum rate interval.
Claim 5
Dependent Claim
121 words
The pacer of claim 1 wherein said rate limit logic includes: monitor means for detecting the state of said input signal; counter means responsive to said clock pulses for producing a first minimum rate interval signal, a second maximum rate interval signal and a third dropout rate interval signal; first logic means responsive to said maximum rate interval signal for gating said input signal to said output signal means when said input signal period exceeds said maximum rate interval; second logic means responsive to said dropout interval signal for preventing counter reset signals from resetting said counter; and third logic means responsive to said dropout interval signal for producing an output rate at a frequency corresponding to said minimum rate interval.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-05 | 1986-01-04 | 1986-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-05 | 1990-01-04 | 1990-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-05 | 1994-01-04 | 1994-07-06 | $7700.00 | Window Closed / Lapsed |