Method and circuit for controlling a band display of a plurality of analog signals using a single anode type bar graph device

Claim 3

A method as claimed in claim 1, wherein a light spot of a specified length displaying the value of a first analog signal is provided on the display scale by a first level of light intensity, a substantially uniform light column displaying the value of a second analog signal is provided on the display scale by a second, middle, level of light intensity, and a separation is provided on the display scale between the first analog signal display and the second analog signal display by a third level of light intensity.

Claim 4

A method as claimed in claim 2, wherein the first level of light intensity is produced by decreasing the scanning speed of said display elements with regard to the second level and the third level of light intensity and by decreasing the current supply to said display elements with regard to said second level of light intensity.

Claim 5

A method as claimed in claim 3, wherein the display device comprises a phase-controlled gas discharge tube having cathodes, an anode and a cathode control, the first level of light intensity is produced by extending the phase durations of the cathode control of the gas discharge tube and the third level of light intensity is produced by restricting the anode current of the tube to a level corresponding to the minimum energy required for a discharge transfer.

Claim 6

A control circuit for a band display of at least two analog signals wherein first and second analog signals are displayed, said control circuit comprising a sawtooth generator having an input and first and second outputs and providing sawtooth and reset signals at the first and second outputs, respectively; a first comparator circuit having an output, a first input to which the first analog signal is supplied and a second input connected to the first output of said sawtooth generator, said first comparator comparing said first analog signal with said first sawtooth signal and providing at its output a pulse for forming the display; display means having display elements; deceleration duration means for defining the scanning speed deceleration duration of the display elements, said deceleration duration means having an output and an input connected to the output of said first comparator circuit; a phase duration circuit having a first input connected to the output of said deceleration duration means, a second input, a first output and a second output coupled to the display means, said phase duration circuit defining the scanning speed of the display elements under the control of said deceleration duration means; sawtooth generator stopping means having a first input connected to the output of said deceleration duration means, a second input connected to the first output of said phase duration circuit and an output connected to the input of said sawtooth generator, said sawtooth generator stopping means decelerating an increase of said sawtooth signal; a second comparator circuit having an output, a first input to which the second analog signal is supplied and a second input connected to the first output of said sawtooth generator, said second comparator circuit comparing said second analog signal with said sawtooth signal and providing at its output a pulse for forming the display; and current restricting means having an output connected to the display elements of the display means and an input coupled to the output of said second comparator circuit, said current restricting means restricting the current of said display elements under the control of the output pulse of said second comparator circuit.

Claim 7

A control circuit for a band display of at least two analog signals wherein first and second analog signals are displayed, said control circuit comprising a sawtooth generator having an input and first and second outputs and providing sawtooth and reset signals at the first and second outputs, respectively; a first comparator circuit having an output, a first input to which the first analog signal is supplied and a second input connected to the first output of said sawtooth generator, said first comparator comparing said first analog signal with said first sawtooth signal and providing at its output a pulse for forming the display; display means having display elements; deceleration duration means for defining the scanning speed deceleration duration of the display elements, said deceleration duration means having an output and an input connected to the output of said first comparator circuit; a phase duration circuit having a first input connected to the output of said deceleration duration means, a second input, a first output and a second output coupled to the display means, said phase duration circuit defining the scanning speed of the display elements under the control of said deceleration duration means; sawtooth generator stopping means having a first input connected to the output of said deceleration duration means, a second input connected to the first output of said phase duration circuit and an output connected to the input of said sawtooth generator, said sawtooth generator stopping means decelerating an increase of said sawtooth signal; a second comparator circuit having an output, a first input to which the second analog signal is supplied and a second input connected to the first output of said sawtooth generator, said second comparator circuit comparing said second analog signal with said sawtooth signal and providing at its output a pulse for forming the display; and current restricting means having an output connected to the display elements of the display means and an input coupled to the output of said second comparator circuit, said current restricting means restricting the current of said display elements under the control of the output pulse of said second comparator circuit.

Claim 8

A control circuit as claimed in claim 5, wherein said display means comprises a phase-controlled gas discharge tube having phase cathodes and display elements scanned by cyclical control of the phase cathodes in alternating phases, and further comprising cathode control means for defining the control frequency of said phase cathodes, said cathode control means comprising a clock oscillator having an output and an input connected to the second output of said sawtooth generator and said phase duration circuit, the second input of said phase duration circuit being connected to the output of said clock oscillator, said clock oscillator and phase duration circuit providing phase pulses at the second output of said phase duration circuit, and a control and phase exchange circuit for said phase cathodes, said control and phase exchange circuit having a first input connected to the second output of said sawtooth generator, a second input connected to the second output of said phase duration circuit and an output connected to said gas discharge tube whereby said phase duration circuit is coupled to said gas discharge tube via said control and phase exchange circuit.

Claim 9

A control circuit as claimed in claim 6, wherein said current restricting means includes a switching transistor controlled by said phase pulses.

Claim 10

A control circuit as claimed in claim 6, wherein the display elements of said gas discharge tube comprise two display scales, and further comprising a scale selector circuit connected between the second output of said sawtooth generator and the display scales of said gas discharge tube, said scale selector circuit being changed in state by said reset signal at the beginning of the operating cycle of said sawtooth generator.

Claim 11

A control circuit as claimed in claim 6, wherein said reset signal locks said clock oscillator, said phase duration circuit and the cathodes of said gas discharge tube via said control and phase exchange circuit.

Claim 12

A control circuit as claimed in claim 6, wherein said phase duration circuit includes a frequency distributor and said control and phase exchange circuit controls the cathodes of said gas discharge tube via a frequency defined by said clock oscillator and the frequency distributor of said phase duration circuit.

Claim 13

A control circuit as claimed in claim 6, wherein said deceleration duration means includes a counter connected to the second output of said phase duration circuit and controlled by said phase pulses, said counter being preset to the number of phases to be decelerated.