US4335505A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing semiconductor memory device having memory cell elements composed of a transistor and a capacitor
Assignee: Mitsubishi Electric Corp
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Filing: 1979-12-26
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Granted: 1982-06-22
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Expires: 1999-12-26
Abstract
Abstract A method for forming semiconductor memory devices each including either an MNOS-type or MOS-type transistor and an MNOS-type capacitor. Upon a silicon substrate there is formed a thick layer of oxide which defines the individual cells and provides separation therebetween. Exposed portions of the substrate are thermally oxidized to form a layer of thermal oxide upon which is subsequently deposited a layer of silicon nitride and a layer of polycrystalline silicon. The polycrystalline silicon is then masked and portions there are removed through apertures and the mask. The substrate is then irradiated at a non-perpendicular angle through the apertures in the mask and predetermined remaining portions of the layer of thermal oxide are removed. Exposed portions of the substrate at this point are diffused with an impurity of the opposite conductivity type to the substrate. A second polycrystalline silicon layer is then formed to provide bit lines for each memory cell and simultaneously an opposing electrode of the corresponding capacitors. A second thick oxide layer is then formed with a metal interconnection layer deposited thereon for forming the connection lines to each memory cell.
Inventors
- 👤 Hiroshi Shibata
- 👤 Tatsuya Enomoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:15
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
260 words
A method for producing a semiconductor memory device including multiple memory cell elements, each cell being composed of a transistor and a capacitor, comprising the steps of: providing a substrate of silicon having a first conductivity type; forming a first thick layer of oxide on a surface of said substrate in a predetermined pattern for providing separation between adjacent memory cell elements; thermally oxidizing exposed portions of said surface of said substrate to form a layer of thermal oxide; depositing a layer of silicon nitride over said layer of thermal oxide and said thick layer of oxide; depositing a first layer of polycrystalline silicon over said layer of silicon nitride; forming a layer of photoresist over said layer of polycrystalline silicon in a predetermined pattern; removing portions of said first layer of polycrystalline silicon exposed through apertures in said layer of photoresist; irradiating said substrate at a non-perpendicular angle through apertures in said photoresist layer; removing said photoresist layer and predetermined remaining portions of said layer of thermal oxide; providing impurities having a second conductivity type to portions of said substrate exposed through said steps of irradiating; removing said layer of polycrystalline silicon in predetermined regions so as to form bit lines for each memory cell and opposing electrode of each said capacitor; oxidizing exposed regions of said substrate and said layer of polycrystalline silicon to form second thick oxide layers; forming a layer of metal over uppermost layers or said surface of said substrate; and etching said layer of metal to form connection lines to each said memory cell.
Claim 2
Independent Claim
260 words
A method for producing a semiconductor memory device including multiple memory cell elements, each cell being composed of a transistor and a capacitor, comprising the steps of: providing a substrate of silicon having a first conductivity type; forming a first thick layer of oxide on a surface of said substrate in a predetermined pattern for providing separation between adjacent memory cell elements; thermally oxidizing exposed portions of said surface of said substrate to form a layer of thermal oxide; depositing a layer of silicon nitride over said layer of thermal oxide and said thick layer of oxide; depositing a first layer of polycrystalline silicon over said layer of silicon nitride; forming a layer of photoresist over said layer of polycrystalline silicon in a predetermined pattern; removing portions of said first layer of polycrystalline silicon exposed through apertures in said layer of photoresist; irradiating said substrate at a non-perpendicular angle through apertures in said photoresist layer; removing said photoresist layer and predetermined remaining portions of said layer of thermal oxide; providing impurities having a second conductivity type to portions of said substrate exposed through said steps of irradiating; removing said layer of polycrystalline silicon in predetermined regions so as to form bit lines for each memory cell and opposing electrode of each said capacitor; oxidizing exposed regions of said substrate and said layer of polycrystalline silicon to form second thick oxide layers; forming a layer of metal over uppermost layers or said surface of said substrate; and etching said layer of metal to form connection lines to each said memory cell.
Claim 3
Independent Claim
270 words
A method for producing a semiconductor memory device including multiple memory cell elements, each cell being composed of a transistor and a capacitor, comprising the steps of: providing a substrate of silicon having a first conductivity type; forming a first thick layer of oxide on a surface of said substrate in a predetermined pattern for providing separation between adjacent memory cell elements; thermally oxidizing exposed portions of said surface of said substrate to form a layer of thermal oxide; depositing a layer of silicon nitride over said layer of thermal oxide and said thick layer of oxide; depositing a layer of polycrystalline silicon over said layer of silicon nitride; forming a layer of photoresist over said layer of polycrystalline silicon in a predetermined pattern; removing portions of said first layer of polycrystalline silicon exposed through apertures in said layer of photoresist; irradiating said substrate at a non-perpendicular angle through apertures in said photoresit layer; removing said photoresist layer and predetermined removing portions of said layer of thermal oxide; providing impurities having a second conductivity type to portions of said substrate exposed through said steps of irradiating; removing said layer of polycrystalline silicon layers in predetermined regions so as to form bit lines for each said memory cell and an opposing electrode of each said capacitor; removing predetermined portions of said layer of silicon nitride and said layer of thermal oxide; forming a thin oxide film over uppermost layers on said substrate; forming a layer of metal over uppermost layers on said surface of said substrate; and etching said layer of metal to form connection lines to each said memory cell.
Claim 4
Independent Claim
270 words
A method for producing a semiconductor memory device including multiple memory cell elements, each cell being composed of a transistor and a capacitor, comprising the steps of: providing a substrate of silicon having a first conductivity type; forming a first thick layer of oxide on a surface of said substrate in a predetermined pattern for providing separation between adjacent memory cell elements; thermally oxidizing exposed portions of said surface of said substrate to form a layer of thermal oxide; depositing a layer of silicon nitride over said layer of thermal oxide and said thick layer of oxide; depositing a layer of polycrystalline silicon over said layer of silicon nitride; forming a layer of photoresist over said layer of polycrystalline silicon in a predetermined pattern; removing portions of said first layer of polycrystalline silicon exposed through apertures in said layer of photoresist; irradiating said substrate at a non-perpendicular angle through apertures in said photoresit layer; removing said photoresist layer and predetermined removing portions of said layer of thermal oxide; providing impurities having a second conductivity type to portions of said substrate exposed through said steps of irradiating; removing said layer of polycrystalline silicon layers in predetermined regions so as to form bit lines for each said memory cell and an opposing electrode of each said capacitor; removing predetermined portions of said layer of silicon nitride and said layer of thermal oxide; forming a thin oxide film over uppermost layers on said substrate; forming a layer of metal over uppermost layers on said surface of said substrate; and etching said layer of metal to form connection lines to each said memory cell.
Claim 5
Independent Claim
23 words
A method as claimed in any of claims 1 or 2 wherein said irradiating is carried out by means of a light beam.
Claim 6
Independent Claim
23 words
A method as claimed in any of claims 1 or 2 wherein said irradiating is carried out by means of an X-ray beam.
Claim 7
Independent Claim
25 words
A method as claimed in any of claims 1 or 2 wherein said irradiating is carried out by means of a beam of charged particles.
Claim 8
Independent Claim
42 words
A method as claimed in any of claims 1 or 2 wherein said oxidizing is carried out by heating said substrate in an oxidizing atmosphere at a pressure greater than 1 atmosphere and at a temperature of no greater than 900° C.
Claim 9
Independent Claim
36 words
A method as claimed in any of claims 1 or 2 further comprising following said step of forming said thin oxide film, the step of forming a layer of silicon nitride on said thin oxide film.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-21 | 1985-12-21 | 1986-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-21 | 1989-12-21 | 1990-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-21 | 1993-12-21 | 1994-06-22 | $7700.00 | Window Closed / Lapsed |