Printer system having parity checking of print hammers using software control

Claim 1

In a printer system, the combination comprising a plurality of print hammers and a plurality of operating circuits operable for individually actuating said plurality of said print hammers; a moving type belt or the like having characters alignable with said hammers in a plurality of subscan sequence arrangements; and a printer control means for selectively operating said print hammers in timed relation with the alignment of said characters with said print hammers including print hammer selection means connected to said operating circuits and operable in a plurality of successive subscans for selectively activating various combinations of said operating circuits in accordance with said sequence arrangements; and checking means for periodically checking the condition of said operating circuits including parity circuit means operatively connected with said operating circuits and operable in response to the operative condition of said operating circuits for generating an actual parity signal indicative of the actual condition of said operating circuits, said actual parity signal from said parity circuit means being continuously updated by said parity circuit means in response to changes in the operative condition of said operating circuits resulting from the operation of said print hammer selection means in the activation and deactivation of said operating circuits in the course of a plurality of subscans, said actual parity signal from said parity circuit means representing the instantaneous operative condition of said plurality of operating circuits, storage means for storing expected parity information representing print hammers to be activated for each of said plurality of subscans, processor means connected to said storage means for periodically deriving composite parity information from said expected parity information in said storage means for said plurality of subscans, said derived composite parity information representing the expected condition of said plurality of operating circuits for said plurality of subscans, and means controlled by said processor means for periodically comparing said actual parity signal from said parity circuit means with said derived composite parity information for said plurality of said subscans and for providing an error signal in the event of an inequality between said actual parity signal and said derived composite parity information.