Memory control system

Claim 2

A memory control system comprising a memory supplied with an digital signal comprising a series of data; and a control circuit for producing a control signal to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality (k) of memory capacity segments having given capacity values (lengths) which are different from each other, and said digital signal is written in datum by datum with an order and further the written-in digital signal is read out datum by datum with an order rearranged from the order with which the digital signal is written in, by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 3

A memory control system as claimed in claim 1 in which said control circuit controls write-in and read-out operations at the same rate while satisfying the following equations for write-in address Awi and read-out address Ari ##EQU13## where, i=0 through k-1, D: interleaving length, A: count of a counter for counting write-in clock pulses.

Claim 4

A memory control system as claimed in claim 2, in which said control circuit comprises: a first 2 N system counter for counting the write-in clock pulses for said memory; a first adder for adding the output signal of said first 2 N system counter and the output signal of a first decoder, the resulting added signal values being the write-in address values Awi for said memory; a second 2 N system counter for counting the read-out clock pulses for said memory; and a second adder for adding the output signal of said second 2 N system counter and the output signal of a second decoder, the resulting added signal values being the read-out address values Ari for said memory.

Claim 5

A memory control system comprising a memory supplied with a digital signal comprising a series of data arranged with an order which is different from its original order; and a control circuit for producing a control signal so as to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality (k) of memory capacity segments having given values (lengths) which are different from each other, and said digital signal is written in datum by datum with the order which is different from its original order and further the written-in digital signal is read out datum by datum with the same order as the original order by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 6

A memory control system comprising a memory supplied with a digital signal comprising a series of data arranged with an order which is different from its original order; and a control circuit for producing a control signal so as to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality (k) of memory capacity segments having given values (lengths) which are different from each other, and said digital signal is written in datum by datum with the order which is different from its original order and further the written-in digital signal is read out datum by datum with the same order as the original order by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 7

A memory control system as claimed in claim 4 in which said control circuit controls write-in and read-out operations at the same rate with satisfying the following equations for write-in address Aw'i and read-out address Ar'i: ##EQU14## where, i=0 through k-1 D: interleaving length A: count of a counter for counting write-in clock pulses.

Claim 8

A memory control system as claimed in claim 5 in which said control circuit comprises: a first 2 N system counter for counting the write-in clock pulses for said memory; a first adder for adding the output signal of said 2 N system counter and the output signal of a first decoder, the resulting added signal values being the write-in address values Aw'i for said memory; a second 2 N system counter for counting the read-out clock pulses for said memory; and a second adder for adding the output signal of a second decoder, the resulting added signal values being the read-out address values Ar'i for said memory.

Claim 9

A memory control system comprising a memory supplied with a digital signal comprising a series of data; and a control circuit for producing a control signal so as to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality (k) of memory capacity segments having given values (lengths) which are different from each other, each of the plurality of memory capacity segments including therein a memory capacity part for time axis conversion, all the memory capacity parts having the same capacity value (length), and said digital signal is written-in datum by datum with an order in the divided memory capacity segments other than the memory capacity parts for time axis conversion, and further the written-in digital signal is read out datum by datum from the memory capacity parts for time axis conversion with an order rearranged from the order with which said digital signal is written in, by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 10

A memory control system comprising a memory supplied with a digital signal comprising a series of data; and a control circuit for producing a control signal so as to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality (k) of memory capacity segments having given values (lengths) which are different from each other, each of the plurality of memory capacity segments including therein a memory capacity part for time axis conversion, all the memory capacity parts having the same capacity value (length), and said digital signal is written-in datum by datum with an order in the divided memory capacity segments other than the memory capacity parts for time axis conversion, and further the written-in digital signal is read out datum by datum from the memory capacity parts for time axis conversion with an order rearranged from the order with which said digital signal is written in, by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 11

A memory control system comprising a memory supplied with a digital signal comprising a series of data arranged with an order which is different from its original order; and a control circuit for producing a control signal so as to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality (k) of memory capacity segments having given values (lengths) which are different from each other, each of the plurality of memory capacity segments including therein a memory capacity parts for time axis conversion, all the memory capacity parts having the same capacity value (length), and said digital signal is written in datum by datum in the divided memory capacity segments other than the memory capacity parts for time axis conversion with the order which is different from its original order, and further the written-in digital signal is read out datum by datum from the memory capacity parts for time axis conversion with the same order as the original order by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 12

A memory control system comprising a memory supplied with a digital signal comprising a series of data arranged with an order which is different from its original order; and a control circuit for producing a control signal so as to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality (k) of memory capacity segments having given values (lengths) which are different from each other, each of the plurality of memory capacity segments including therein a memory capacity parts for time axis conversion, all the memory capacity parts having the same capacity value (length), and said digital signal is written in datum by datum in the divided memory capacity segments other than the memory capacity parts for time axis conversion with the order which is different from its original order, and further the written-in digital signal is read out datum by datum from the memory capacity parts for time axis conversion with the same order as the original order by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 13

A memory control system comprising a memory supplied with a digital signal comprising a series of data arranged with an order which is different from its original order; and a control circuit for producing a control signal so as to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality (k) of memory capacity segments having given values (lengths) which are different from each other, each of the plurality of memory capacity segments including therein a memory capacity part for time axis conversion and for compensation of time axis fluctuation, all the memory capacity parts having the same capacity value (length), and said digital signal is written in datum by datum in the divided memory capacity segments other than the memory capacity parts for time axis conversion and for compensation of time axis fluctuation with the order which is different from its original order, and further the written-in digital signal is read out datum by datum from the memory capacity parts for time axis conversion and for compensation of time axis fluctuation with the same order as the original order by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 14

A memory control system comprising a memory supplied with a digital signal comprising a series of data arranged with an order which is different from its original order; and a control circuit for producing a control signal so as to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality (k) of memory capacity segments having given values (lengths) which are different from each other, each of the plurality of memory capacity segments including therein a memory capacity part for time axis conversion and for compensation of time axis fluctuation, all the memory capacity parts having the same capacity value (length), and said digital signal is written in datum by datum in the divided memory capacity segments other than the memory capacity parts for time axis conversion and for compensation of time axis fluctuation with the order which is different from its original order, and further the written-in digital signal is read out datum by datum from the memory capacity parts for time axis conversion and for compensation of time axis fluctuation with the same order as the original order by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 15

A memory control system as claimed claim 9 in which said control circuit produces a control signal which satisfies the following equations for write-in address Aw"i and read-out address Ar"i of said memory: ##EQU15## where, α: length of said memory capacity parts for time axis conversion and for compensation of time axis fluctuation, i=0 through k-1, α/2: positive integer, D: interleaving length, A: count of a counter for counting write-in clock pulses, A': count of a counter for counting read-out clock pulses.

Claim 16

A memory control system as claimed in claim 10 in which said control circuit comprises: a first 2 N system counter for counting write-in clock pulses which have the same time axis fluctuation as that in the digital signal supplied to said memory; a first adder for adding the output signal of said first 2 N system counter and the output signal of a first decoder, the resulting added signal values being the write-in address value Aw"i for said memory; a second 2 N system counter for counting read-out clock pulses which are free from the time axis fluctuation; and a second adder for adding the output signal of said second 2 N system counter and the output signal of a second decoder, the resulting added signal values being the read-out address value Ar"i for said memory.

Claim 17

A memory control system comprising a memory supplied with a digital signal composed of a series of blocks, each of which comprises elements of a predetermined number of data arranged with an order which is different from its original order and an element of a correction signal formed from the predetermined number of data which are arranged with the original order; and a control circuit for producing a control signal so as to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality of memory capacity segments having given values (lengths) which are different from each other, all of the plurality of memory capacity segments other than the memory capacity segments for said correction signal including therein memory capacity parts for compensating for time axis fluctuation, all said parts having the same capacity value (length), and said digital signal is written in element by element in the divided memory capacity segments other than the memory capacity parts for compensating for time axis fluctuation with the order which is different its original order and further the written-in digital signal is read out element by element at a rate in synchronism with the time axis fluctuation from the divided memory capacity segments other than the memory capacity parts for compensating for time axis fluctuation with the same order as the original order thereby to correct any erroneous datum by using the read-out correction signal, any datum thus corrected is again written in in the divided memory capacity segment from which said any erroneous datum has been read out, and the error-free data and any datum which has been read out and rewritten are read out datum by datum from the memory capacity parts for compensating for time axis fluctuation with the same order as the original order, by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 18

A memory control system comprising a memory supplied with a digital signal composed of a series of blocks, each of which comprises elements of a predetermined number of data arranged with an order which is different from its original order and an element of a correction signal formed from the predetermined number of data which are arranged with the original order; and a control circuit for producing a control signal so as to control said memory in such a manner that the total memory capacity of said memory is partitioned into a plurality of memory capacity segments having given values (lengths) which are different from each other, all of the plurality of memory capacity segments other than the memory capacity segments for said correction signal including therein memory capacity parts for compensating for time axis fluctuation, all said parts having the same capacity value (length), and said digital signal is written in element by element in the divided memory capacity segments other than the memory capacity parts for compensating for time axis fluctuation with the order which is different its original order and further the written-in digital signal is read out element by element at a rate in synchronism with the time axis fluctuation from the divided memory capacity segments other than the memory capacity parts for compensating for time axis fluctuation with the same order as the original order thereby to correct any erroneous datum by using the read-out correction signal, any datum thus corrected is again written in in the divided memory capacity segment from which said any erroneous datum has been read out, and the error-free data and any datum which has been read out and rewritten are read out datum by datum from the memory capacity parts for compensating for time axis fluctuation with the same order as the original order, by means of circulating addresses through the plurality of divided memory capacity segments while maintaining the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments to be constant.

Claim 19

A memory control system as claimed in claim 12 in which said control circuit produces the control signal for controlling said memory in such a manner that the write-in of the elements of a predetermined number of data which are arranged with an order which is different from its original order and the element of a correction signal in each of the divided memory capacity segments other than the memory capacity parts for compensating for time axis fluctuation, is carried out by specifying an address Awi which satisfies the following equations when i=0 through (m-1), ##EQU16## when i=m through (k-1) ##EQU17## (where D is interleaving length, α is length of the memory capacity part for compensating for time axis fluctuation, m is a number of data in each block, and A is the calculated value of a counter for counting clock pulses for write-in), operation for reading out said correction signal is carried out by specifying an address Ar'i which satisfies the following equations, when i=0 through (m-1), ##EQU18## when i=m through (k-1), ##EQU19## and, read out of data from each of said memory capacity parts for compensating for time axis fluctuation is carried out by specifying an address Ari which satisfies the following equation, ##EQU20## (where, A' is the count of a counter for counting clock pulses for read-out, and α/2 is a positive integer).

Claim 20

A memory control system as claimed in claim 1 or 7 in which said digital signal supplied to said memory is a modulated digital signal which is formed by subjecting an analog signal to digital signal processing of discontinuous level modulation system.

Claim 21

A memory control system as claimed in claim 4, 8, 9 or 12 in which said digital signal supplied to said memory is a digital signal, the data of which have been arranged with an order different from an original order of data of a modulated digital signal which is formed by subjecting an analog signal to digital signal processing of discontinuous level modulation system, and have passed through a transmission system.