US4331930A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bias circuit for power amplifier
Assignee: Trio KK
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Filing: 1980-01-08
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Granted: 1982-05-25
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Expires: 2000-01-08
Abstract
Abstract A bias circuit for single-ended push-pull amplifiers permits class A or class AB operation while substantially reducing the idling current of the output transistors at low input signal levels. The bias circuit includes a DC current limiting circuit comprised of transistors that are connected between the common output of the amplifier and the bases of the output transistors. The transistors of the DC current limiting circuit limit the idling currents of the output transistors when there is no input signal applied to the amplifier. The bias circuit further includes RC/diode circuits which operate to increase or decrease the bias voltages of the transistors of the DC current limiting circuit corresponding to a decrease or an increase of the output voltage of the amplifier. In this way, the idling currents of the output transistors are changed so as to effectively follow the input signal power.
Inventors
- 👤 Isumi Shibata
- 👤 Kazumasa Sakai
- 👤 Nobuyuki Sanpei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:24
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/02; H03F1/0205; H03F1/0261; H03F3/00; H03F3/30; H03F3/3069; H03F3/3071
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
180 words
In a single-ended push-pull amplifier of the type biased so as to perform class A or class AB amplification, said amplifier having first and second output transistors connected to supply a driving current to a load connected to a common output of the amplifier, the improvement in a bias circuit for said amplifier comprising: first and second DC limiting transistors connected respectively between said common output and the bases of said first and second output transistors; first and second biasing means respectively connected to the bases of said first and second DC limiting transistors for supplying a bias voltage corresponding to the output current of said output transistors to thereby limit the idling currents of said output transistors when no input signal is applied to the amplifier; and means connected between said common output and the bases of said first and second DC limiting transistors for changing the idling currents of said first and second output transistors corresponding to a change in the output voltage at said common output whereby the amplifier continuously performs class A or class AB amplification.
Claim 2
Dependent Claim
180 words
In a single-ended push-pull amplifier of the type biased so as to perform class A or class AB amplification, said amplifier having first and second output transistors connected to supply a driving current to a load connected to a common output of the amplifier, the improvement in a bias circuit for said amplifier comprising: first and second DC limiting transistors connected respectively between said common output and the bases of said first and second output transistors; first and second biasing means respectively connected to the bases of said first and second DC limiting transistors for supplying a bias voltage corresponding to the output current of said output transistors to thereby limit the idling currents of said output transistors when no input signal is applied to the amplifier; and means connected between said common output and the bases of said first and second DC limiting transistors for changing the idling currents of said first and second output transistors corresponding to a change in the output voltage at said common output whereby the amplifier continuously performs class A or class AB amplification.
Claim 3
Dependent Claim
93 words
The bias circuit as recited in claim 1, wherein said means for changing the idling currents comprises: first and second capacitors respectively connected between the bases of said first and second DC limiting transistors and said common output; and first and second series circuits each composed of a resistor and a diode and respectively connected between the bases of said first and second DC limiting transistors and ground, the diodes of said first and second series circuits being poled to conduct during alternate half cycles of an AC signal at said common output.
Claim 4
Dependent Claim
91 words
The bias circuit as recited in claim 1, wherein said means for changing the idling currents comprises: first and second series circuits each having a resistor and a diode and respectively connected between the bases of said first and second DC limiting transistors and ground, the diodes of said first and second series circuits being oppositely poled; third and fourth series circuits each having a resistor and a capacitor and respectively connected between the junction of the resistor and diode of said first and second series circuits and said common output.
Claim 5
Dependent Claim
35 words
The bias circuit as recited in claim 3, wherein said means for changing the idling currents further comprises a resistor connected in parallel with the diode in each of said first and second series circuits.
Claim 6
Dependent Claim
151 words
The bias circuit as recited in claim 1, wherein said means for changing the idling currents comprises: first, second, third and fourth series circuits each having a resistor and a diode, the resistors of said first and second series circuits being respectively connected to the bases of said first and second DC limiting transistors and the resistors of said third and fourth series circuits being connected to said common output, the diodes of said first and third series circuits being connected to a first junction and poled in a first direction and the diodes of said second and fourth series circuits being connected to a second junction and poled in a second direction opposite to said first direction; a first capacitor and a first resistor connected in parallel between said first junction and ground; and a second capacitor and a second resistor connected in parallel between said second junction and ground.
Claim 7
Dependent Claim
48 words
The bias circuit as recited in claim 1, wherein each of said first and second output transistors comprise a Darlington pair and each of said first and second biasing means comprises a voltage divider connected between the emitter-base junction of the corresponding Darlington pair and said common output.
Claim 8
Dependent Claim
102 words
In a single-ended push-pull amplifier of the type biased so as to perform class A or class AB amplification, said amplifier having first and second output transistors connected to supply a driving current to a load connected to a common output of the amplifier, the improvement in a bias circuit for said amplifier comprising: means for continuously changing the bias voltages to said output transistors corresponding to changes in the output current of said output transistors, so that the idling currents of the output transistors effectively follow the input signal power whereby the amplifier continuously performs class A or class AB amplification.
Claim 9
Dependent Claim
102 words
In a single-ended push-pull amplifier of the type biased so as to perform class A or class AB amplification, said amplifier having first and second output transistors connected to supply a driving current to a load connected to a common output of the amplifier, the improvement in a bias circuit for said amplifier comprising: means for continuously changing the bias voltages to said output transistors corresponding to changes in the output current of said output transistors, so that the idling currents of the output transistors effectively follow the input signal power whereby the amplifier continuously performs class A or class AB amplification.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-24 | 1985-11-23 | 1986-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-24 | 1989-11-23 | 1990-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-24 | 1993-11-23 | 1994-05-25 | $7700.00 | Window Closed / Lapsed |