US4331885A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate circuit
Assignee: Faurecia Clarion Electronics Co Ltd
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Filing: 1981-02-17
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Granted: 1982-05-25
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Expires: 2001-02-17
Abstract
Abstract A gate circuit comprised of a first gate transistor normally off; a second gate transistor normally on and connected in a signal path; said first gate transistor being adapted to be turned on when a pulse is applied thereto and said second gate transistor being adapted to be turned off upon the conducting of said first gate transistor, and a limiter for holding the potential at the input of the second gate transistor lower than the potential at the output thereof.
Inventors
- 👤 Kiyoshi Amazawa
- 👤 Masaharu Mori
- 👤 Takashi Taniyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:32
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34; H03G3/345
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
319 words
A gate circuit comprising: a signal path in which an input signal having noise signal components is to be fed, said signal path extending between signal input and output terminals; first gate means normally in its off state; second gate means connected in series with said signal path and normally in its on state to allow said signal applied to said signal path to pass therethrough, said first gate means being coupled to said second gate means so that the turning on of said first gate means will turn off said second gate means, said first and second gate means each being a current control device having a control terminal and a pair of load terminals where the current or voltage condition of the control terminal establish a low resistance conduction-on or high resistance conduction-off condition between the load terminals thereof, the load terminals of the device comprising said first gate means being coupled between the control terminal and the load terminal nearest said signal path input terminal of said second gate means so that the conduction-on condition of said first gate means will normally turn off conduction between the load terminals of said second gate means to open said signal path; means for providing a noise-indicating control signal occurring during the noise signal components of said input signal and feeding said control signal to the control terminal of said first gate means to turn it on, thereby allowing said second gate means to be cut off; and limiter means coupled to said load terminal nearest said input terminal of said second gate means and responsive to the potential of the latter load terminal for limiting the input potential of said second gate means to such level as to prevent said second gate means from turning on due to the variation of the input potential voltage when the second gate means is turned off by said first gate means.
Claim 2
Dependent Claim
319 words
A gate circuit comprising: a signal path in which an input signal having noise signal components is to be fed, said signal path extending between signal input and output terminals; first gate means normally in its off state; second gate means connected in series with said signal path and normally in its on state to allow said signal applied to said signal path to pass therethrough, said first gate means being coupled to said second gate means so that the turning on of said first gate means will turn off said second gate means, said first and second gate means each being a current control device having a control terminal and a pair of load terminals where the current or voltage condition of the control terminal establish a low resistance conduction-on or high resistance conduction-off condition between the load terminals thereof, the load terminals of the device comprising said first gate means being coupled between the control terminal and the load terminal nearest said signal path input terminal of said second gate means so that the conduction-on condition of said first gate means will normally turn off conduction between the load terminals of said second gate means to open said signal path; means for providing a noise-indicating control signal occurring during the noise signal components of said input signal and feeding said control signal to the control terminal of said first gate means to turn it on, thereby allowing said second gate means to be cut off; and limiter means coupled to said load terminal nearest said input terminal of said second gate means and responsive to the potential of the latter load terminal for limiting the input potential of said second gate means to such level as to prevent said second gate means from turning on due to the variation of the input potential voltage when the second gate means is turned off by said first gate means.
Claim 3
Dependent Claim
69 words
A gate circuit as set forth in claim 1, wherein said second gate means is comprised of a transistor where said load terminals are the collector and emitter terminals thereof, the collector terminal thereof being the load terminal connected to said signal path input terminal and said first gate means is comprised of another transistor whose load terminals include the collector connected to the base of the former transistor.
Claim 4
Dependent Claim
72 words
A gate circuit as set forth in claim 1, which further comprises a constant current source means connected to the control terminal of said second gate means for supplying a bias current thereto so that the bias current flows following the input signal current of the second gate means when said first gate means turns on in response to said control signal, thereby allowing said second gate means to be turned off.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-24 | 1985-11-23 | 1986-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-24 | 1989-11-23 | 1990-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-24 | 1993-11-23 | 1994-05-25 | $7700.00 | Window Closed / Lapsed |