US4330820A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for forming periodic pulse patterns
Assignee: Siemens AG
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Filing: 1979-06-04
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Granted: 1982-05-18
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Expires: 1999-06-04
Abstract
Abstract A circuit arrangement for the formation of periodic pulse patterns for use in controlling converters which is capable of quick change of circuit arrangement without time wasted in adjustment and capable of use in different applications without need to change circuit. The circuit arrangement of the invention is also useful for the formation of a periodic pulse pattern which is variable as a function of a control signal. For this purpose the desired pulse pattern is formed of auxiliary patterns stored in a number of memories. An oscillator drives a binary-coded counter which forms the addresses for a memory in which the desired pulse pattern is stored. The address inputs of at least one of these memories are connected to the output of the counter by means of an arrangement for address shifting which responds to a control signal.
Inventors
- 👤 Rudiger Braun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:44
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/08; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/505; H02M7/515; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/72; H03K17/73; H03K17/94; H03K3/00; H03K3/78; H03K5/00; H03K5/15; H03K5/15013; H03K5/1502; H03K5/1506; H03K5/15093
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
163 words
A circuit for forming a periodic pulse pattern comprising: an oscillator having an output; a binary-coded counter having an input coupled to the output of the oscillator, the counter having an address signal as an output; a first memory containing a first auxiliary pulse pattern, the memory having the address signal as an input and having an auxiliary periodic pulse pattern as an output; address shifting means comprising at least one of an adder or a subtractor having a first input coupled to the output of the counter and a second input coupled to a number determined by a control signal, the address shifting means having an output signal; a second memory containing a second auxiliary pulse pattern, the second memory having an address input coupled to the output of the address shifting means and having a second auxiliary pulse pattern as an output; and logic means having the outputs of the memories as inputs and having the periodic pulse pattern as outputs.
Claim 2
Dependent Claim
163 words
A circuit for forming a periodic pulse pattern comprising: an oscillator having an output; a binary-coded counter having an input coupled to the output of the oscillator, the counter having an address signal as an output; a first memory containing a first auxiliary pulse pattern, the memory having the address signal as an input and having an auxiliary periodic pulse pattern as an output; address shifting means comprising at least one of an adder or a subtractor having a first input coupled to the output of the counter and a second input coupled to a number determined by a control signal, the address shifting means having an output signal; a second memory containing a second auxiliary pulse pattern, the second memory having an address input coupled to the output of the address shifting means and having a second auxiliary pulse pattern as an output; and logic means having the outputs of the memories as inputs and having the periodic pulse pattern as outputs.
Claim 3
Dependent Claim
33 words
A circuit in accordance with claim 6 and further comprising: a third memory having the control signal as an address input and having the number determined by the control signal as an output.
Claim 4
Dependent Claim
43 words
A circuit in accordance with claims 1 or 2 and further comprising: a static inverter having plural controlled valves each of which has an input for firing pulses, the input of each controlled valve being coupled to an output of the logic means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-17 | 1985-11-16 | 1986-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-17 | 1989-11-16 | 1990-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-17 | 1993-11-16 | 1994-05-18 | $7700.00 | Window Closed / Lapsed |