US4330759A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for generating synchronized timing pulses from binary data signals
Assignee: AT&T Inc
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Filing: 1980-03-05
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Granted: 1982-05-18
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Expires: 2000-03-05
Abstract
Abstract Timing pulses are generated from operative synchronous data pulses by means of a crystal oscillator under direct control of the output signal of a D flip-flop. The flip-flop is set or reset depending on the phase of the clock pulse relative to the leading edge of the data pulse.
Inventors
- 👤 Thomas W. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:31
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
210 words
A clock pulse generating circuit comprising a voltage controlled oscillator having a base frequency and having a control terminal and an output terminal, characterized in that said circuit further comprises clocked bistable means having first and second stable states and having an output terminal directly connected to said control terminal, a first input terminal connected to said oscillatior output terminal, and a second input terminal connectable to a data source; said bistable means being responsive to clock pulses having leading and trailing edges occurring on said first input terminal and data pulses having leading and trailing edges occurring on said second input terminal to apply to said control terminal a first control signal when the leading edge of a data pulse is preceded in time by a predetermined edge of a corresponding clock pulse and a second control signal when the leading edge of a data pulse precedes said predetermined edge of a corresponding clock pulse; said oscillator being responsive to said first control signal to provide a clock signal having a frequency which is less than said base frequency by a predetermined value and responsive to said second control signal to provide a clock signal having a frequency which is greater than said base frequency by a predetermined value.
Claim 2
Dependent Claim
210 words
A clock pulse generating circuit comprising a voltage controlled oscillator having a base frequency and having a control terminal and an output terminal, characterized in that said circuit further comprises clocked bistable means having first and second stable states and having an output terminal directly connected to said control terminal, a first input terminal connected to said oscillatior output terminal, and a second input terminal connectable to a data source; said bistable means being responsive to clock pulses having leading and trailing edges occurring on said first input terminal and data pulses having leading and trailing edges occurring on said second input terminal to apply to said control terminal a first control signal when the leading edge of a data pulse is preceded in time by a predetermined edge of a corresponding clock pulse and a second control signal when the leading edge of a data pulse precedes said predetermined edge of a corresponding clock pulse; said oscillator being responsive to said first control signal to provide a clock signal having a frequency which is less than said base frequency by a predetermined value and responsive to said second control signal to provide a clock signal having a frequency which is greater than said base frequency by a predetermined value.
Claim 3
Dependent Claim
22 words
The clock pulse generating circit in accordance with claim 1 characterized in that said bistable circuit means comprises a D type flip-flop.
Claim 4
Dependent Claim
24 words
The clock pulse generating circuit in accordance with claim 1 characterized in that said predetermined edge is the trailing edge of a clock pulse.
Claim 5
Dependent Claim
40 words
A clock pulse generating circuit in accordance with claim 1 characterized in that said voltage controlled oscillator comprises a crystal oscillator responsive to control signals to produce clock signals of a frequency within a narrow range from said base frequency.
Claim 6
Dependent Claim
37 words
The clock pulse generating circuit in accordance with claim 4 wherein said crystal oscillator is responsive to control signals to provide clock signals having a frequency equal to its base frequency plus or minus approximately 1,000 hertz.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-17 | 1985-11-16 | 1986-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-17 | 1989-11-16 | 1990-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-17 | 1993-11-16 | 1994-05-18 | $7700.00 | Window Closed / Lapsed |