Precision converter/isolation circuit

Claim 2

A converter circuit which generates an output signal (V 2 ) which is identical to a monitored input signal (V 1 ) characterized by: first generating means (101) responsive to the receipt of said input signal (V 1 ) for generating a drive signal (V I ) which contains the following components: a first error signal (V BE1 ) and said input signal (V 1 ); second generating means (103) connected to said first generating means (101) and responsive to said drive signal (V I ) for generating an output signal (V 2 ) which contains the following components: a second error signal (V BE2 ) and said drive signal (V I ), wherein said second error signal (V BE2 ) is in the opposite sense of said first error signal (V BE1 ); compensation means (102) connected to both said first (101) and said second (103) generating means and responsive to said drive signal (V I ) for equalizing said second error signal (V BE2 ) and said first error signal (V BE1 ), to thereby cancel each other in said output signal (V 2 ).

Claim 3

The invention of claim 1 characterized in that said compensation means includes: matched current generating means (112a, 112b) directly connected to said first generating means (101) and responsive to said drive signal (V I ) for generating a first and a second matched currents and for applying said first matched current to said first generating means (101); coupling means (113a) connected to both said matched current generating means (112a, 112b) and said second generating means (103), responsive to said second matched current for controlling the magnitude of said second error signal (V BE2 ); and wherein said first generating means (101) are responsive to said first matched current for controlling the magnitude of said first error signal (V BE1 ).

Claim 4

The invention of claim 2 characterized in that said first generating means (101) comprises a first unity gain isolation amplifier (111), responsive to said input signal (V 1 ) for generating a drive signal which comprises said first error signal (V BE1 ) and said input signal (V 1 ).

Claim 5

The invention of claim 3 characterized in that said second generating means (103) comprises a second unity gain isolation amplifier (113b), responsive to said drive signal (V I ) for generating an output signal (V 2 ) comprising: said input signal (V 1 ), said first error signal (V BE1 ), and said second error signal (V BE2 ).

Claim 6

The invention of claim 4 characterized in that said first unity gain isolation amplifier (111) comprises a voltage amplifier consisting of a PNP transistor (111) connected in the common collector mode with the base terminal connected to said input signal (V 1 ) and the emitter terminal connected to said second generating means (103) and said drive signal (V I ) comprises a voltage equal to said input signal (V 1 ) plus the base-emitter voltage drop (V BE1 ) of said PNP transistor (111).

Claim 7

The invention of claim 5 characterized in that said second unity gain isolation amplifier (113b) comprises a NPN transistor (113b) connected in the common emitter mode with the base terminal connected to said emitter of said PNP transistor (111), the emitter terminal connected to circuit output (105), and said output signal (V 2 ) comprises a voltage equal to said drive signal (V I ) and the base-emitter voltage drop (V BE2 ) of said NPN transistor (113b).

Claim 8

The invention of claim 6 characterized in that said matched current generating means (112a, 112b) comprises current mirror means (112a, 112b) for generating said first and said second matched currents.

Claim 9

The invention of claim 7 characterized in that said coupling means 113a includes a second NPN transistor (113a) connected in the common emitter mode with the base terminal connected to said emitter terminal of said PNP transistor (111), wherein the base-emitter voltage drop of said second NPN transistor (113a) is matched to the base-emitter voltage drop (V BE2 ) of said first NPN transistor (113b).

Claim 10

The invention of claim 8 characterized in that one leg (112b) of said current mirror means is connected to said collector terminal of said second NPN transistor (113a) for supplying said second NPN transistor (113a) with said second matched current and the other leg (112a) of said current mirror means is connected to said emitter terminal of said PNP transistor (111) for supplying said PNP transistor (111) with said first matched current; wherein said PNP transistor (111) and said second NPN transistor (113a) are responsive to said first and said second matched currents respectively for equalizing the base-emitter voltage drops (V BE1 , V BE2 ) of both said PNP (111) and said second NPN (113a) transistors.

Claim 11

The invention of claim 9 characterized in that said compensation means (102) includes first impedance means (114a) connected between said emitter terminal of said second NPN transistor (113a) and circuit ground; said second generating means (103) includes second impedance means (114b) equal in value to said first impedance means (114a) connected in series with said emitter terminal of said first NPN transistor (113b) for providing identical emitter to ground voltages for both said first (113b) and said second (113a) NPN transistors.

Claim 12

A converter circuit which generates an output signal (V 2 ) identical to a monitored input signal (V 1 ) characterized by: PNP transistor means (111) for generating a drive signal (V I ) at the emitter of said PNP transistor means (111) comprising said monitored input signal (V 1 ) and a first error signal (V BE1 ), wherein said PNP transistor means (111) is connected in a common collector configuration with the base of said PNP transistor means (111) being connected to said monitored input signal (V 1 ); NPN transistor means (113b) responsive to said drive signal (V I ) for generating an output comprising said drive signal (V I ) and a second error signal (V BE2 ), with said second error signal (V BE2 ) being in the opposite sense of said first error signal (V BE1 ), wherein said NPN transistor means (113b) is connected in the common emitter configuration with the base of said NPN transistor means (113b) being connected to the emitter of said PNP transistor means (111), and the collector of said NPN transistor means (113b) being connected to a source of power (+V); and compensation means (102) connected to said base of said NPN transistor means (113b) for equalizing said first (V BE1 ) and said second (V BE2 ) error signals such that said NPN transistor means (113b) generates an output (V 2 ) comprising said input signal (V 1 ).

Claim 13

A converter circuit which generates an output signal (V 2 ) identical to a monitored input signal (V 1 ) characterized by: PNP transistor means (111) for generating a drive signal (V I ) at the emitter of said PNP transistor means (111) comprising said monitored input signal (V 1 ) and a first error signal (V BE1 ), wherein said PNP transistor means (111) is connected in a common collector configuration with the base of said PNP transistor means (111) being connected to said monitored input signal (V 1 ); NPN transistor means (113b) responsive to said drive signal (V I ) for generating an output comprising said drive signal (V I ) and a second error signal (V BE2 ), with said second error signal (V BE2 ) being in the opposite sense of said first error signal (V BE1 ), wherein said NPN transistor means (113b) is connected in the common emitter configuration with the base of said NPN transistor means (113b) being connected to the emitter of said PNP transistor means (111), and the collector of said NPN transistor means (113b) being connected to a source of power (+V); and compensation means (102) connected to said base of said NPN transistor means (113b) for equalizing said first (V BE1 ) and said second (V BE2 ) error signals such that said NPN transistor means (113b) generates an output (V 2 ) comprising said input signal (V 1 ).

Claim 14

A converter circuit which generates an output signal (I 2 ) which is directly proportional to a monitored input signal (V 1 ) characterized by: first generating means (101) responsive to the receipt of said input signal (V 1 ) for generating a drive signal (V I ) which contains the following components: a first error signal (V BE1 ) and said input signal (V 1 ); second generating means (103) connected to said first generating means (101) and responsive to said drive signal (V I ) for generating an output signal (I 2 ) which is proportional to an intermediate signal V 2 which contains the following components: A second error signal (V BE2 ) and said drive signal (V I ), wherein said second error signal (V BE2 ) is in the opposite sense of said first error signal (V BE1 ); compensation means (102) connected to both said first (101) and said second (103) generating means and responsive to said drive signal (V I ) for equalizing said second error signal (V BE2 ) and said first error signal (V BE1 ), to thereby cancel each other in said intermediate signal (V 2 ).

Claim 15

A converter circuit which generates an output signal (I 2 ) which is directly proportional to a monitored input signal (V 1 ) characterized by: first generating means (101) responsive to the receipt of said input signal (V 1 ) for generating a drive signal (V I ) which contains the following components: a first error signal (V BE1 ) and said input signal (V 1 ); second generating means (103) connected to said first generating means (101) and responsive to said drive signal (V I ) for generating an output signal (I 2 ) which is proportional to an intermediate signal V 2 which contains the following components: A second error signal (V BE2 ) and said drive signal (V I ), wherein said second error signal (V BE2 ) is in the opposite sense of said first error signal (V BE1 ); compensation means (102) connected to both said first (101) and said second (103) generating means and responsive to said drive signal (V I ) for equalizing said second error signal (V BE2 ) and said first error signal (V BE1 ), to thereby cancel each other in said intermediate signal (V 2 ).

Claim 16

The invention of claim 12 characterized in that said compensation means includes: matched current generating means (112a, 112b) directly connected to said first generating means (101) and responsive to said drive signal (V I ) for generating a first and a second matched currents and for applying said first matched current to said first generating means (101); coupling means (113a) connected to both said matched current generating means (112a, 112b) and said second generating means (103), responsive to said second matched current for controlling the magnitude of said second error signal (V BE2 ); and wherein said first generating means (101) are responsive to said first matched current for controlling the magnitude of said first error signal (V BE1 ).

Claim 17

The invention of claim 13 characterized in that said first generating means (101) comprises a unity gain isolation amplifier (111) consisting of a PNP transistor (111) connected in the common collector mode with the base terminal connected to said input signal (V 1 ) and the emitter terminal connected to said second generating means (103) responsive to said input signal (V 1 ) for generating said drive signal (V I ) comprising a voltage equal to said input signal (V 1 ) plus the base-emitter voltage drop (V BE1 ) of said PNP transistor (111).

Claim 18

The invention of claim 14 characterized in that said second generating means (103) comprises a unity gain isolation amplifier (113b) consisting of a NPN transistor (113b) connected in the common emitter mode with the base terminal connected to said emitter of said PNP transistor (111), the emitter terminal connected to circuit output (105), responsive to said drive signal (V I ) for gennerating said output signal (I 2 ) comprising a current directly proportional to said drive signal (V I ) and the base-emitter voltage drop (V BE2 ) of said NPN transistor (113b).

Claim 19

The invention of claim 15 characterized in that said matched current generating means (112a, 112b) comprises current mirror means (112a, 112b) for generating said first and said second matched currents.

Claim 20

The invention of claim 16 characterized in that said coupling means (113a) includes a second NPN transistor (113a) connected in the common emitter mode with the base terminal connected to said emitter terminal of said PNP transistor (111), wherein the base-emitter voltage drop of said second NPN transistor (113a) is matched to the base-emitter voltage drop (V BE2 ) of said first NPN transistor (113b).

Claim 21

The invention of claim 17 characterized in that one leg (112b) of said current mirror means is connected to said collector terminal of said second NPN transistor (113a) for supplying said second NPN transistor (113a) with said second matched current and the other leg (112a)of said current mirror means is connected to said emitter terminal of said PNP transistor (111) for supplying said PNP transistor (111) with said first matched current; wherein said PNP transistor (111) and said second NPN transistor (113a) are responsive to said first and said second matched currents respectively for equalizing the base-emitter voltage drops (V BE1 , V BE2 ) of both said PNP (111) and said second NPN (113a) transistors.

Claim 22

The invention of claim 18 characterized in that said compensation means (102) includes first impedance means (114a) connected between said emitter terminal of said second NPN transistor (113a) and circuit ground; said second generating means (103) includes second impedance means (114b) equal in value to said first impedance means (114a) connected in series with said emitter terminal of said first NPN transistor (113b) for providing identical emitter to ground voltages for both said first (113b) and said second (113a) NPN transistors.