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US4326208A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor inversion layer transistor

Assignee: International Business Machines Corp
•
Filing: 1980-03-26
•
Granted: 1982-04-20
•
Expires: 2000-03-26
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Abstract

Abstract A semiconductor inversion layer transistor which is compatible with semiconductor fabrication technology, and an integrated circuit which incorporates a plurality of such transistors. In one embodiment of the transistor, a P type indium arsenide base and a P type gallium antimonide emitter are used while the collector can be made of either P type gallium antimonide or N type indium arsenide. By the nature of the band alignment at the interface, the indium arsenide base has its Fermi level pinned in the conduction ban at the base-emitter junction and an assymetrically conducting charge barrier which is formed at this junction is preferential to injection of carriers flowing from the emitter to the base rather than vice versa. When the base-emitter junction is forward biased the electrons at the junction are projected across the base with minimal hole injection from base to emitter, thus providing a high gain transistor having excellent high frequency characteristics.

Inventors

  • 👤 Frank F. Fang
  • 👤 George A. Sai-Halasz

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 14:07
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/82; H10D62/824; H10D10/00; H10D10/80; H10D10/821; H10D10/841

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 129 words
A semiconductor transistor which is comprised of a semiconductor base which is disposed between and which forms respective junctions with a semiconductor emitter and a semiconductor collector, all of said base, emitter and collector being doped with one of donors or acceptors and said junctions having charge barriers associated therewith, at least the base-emitter charge barrier being assymmetrically conducting with respect to electrons and holes respectively, and said emitter and base being of respective semiconductor materials such that the Fermi level in the base is above the conduction band edge or below the valence band edge of said semiconductor material at the base-emitter junction but is in the forbidden band in the interior of the base, whereby an inversion layer is formed in the base at said base-emitter junction.
Claim 2
Dependent Claim 129 words
A semiconductor transistor which is comprised of a semiconductor base which is disposed between and which forms respective junctions with a semiconductor emitter and a semiconductor collector, all of said base, emitter and collector being doped with one of donors or acceptors and said junctions having charge barriers associated therewith, at least the base-emitter charge barrier being assymmetrically conducting with respect to electrons and holes respectively, and said emitter and base being of respective semiconductor materials such that the Fermi level in the base is above the conduction band edge or below the valence band edge of said semiconductor material at the base-emitter junction but is in the forbidden band in the interior of the base, whereby an inversion layer is formed in the base at said base-emitter junction.
Claim 3
Dependent Claim 28 words
The transistor of claim 1, wherein said base and emitter are either comprised of indium arsenide and gallium antimonide respectively or of gallium antimonide and indium arsenide respectively.
Claim 4
Dependent Claim 25 words
The transistor of claim 2, wherein said base is comprised of P type indium arsenide and said emitter is comprised of P type gallium antimonide.
Claim 5
Dependent Claim 20 words
The transistor of claim 3, wherein said base-collector junction is also assymmetrically conducting with respect to electrons and holes respectively.
Claim 6
Dependent Claim 15 words
The transistor of claim 4, wherein said collector is comprised of P type gallium antimonide.
Claim 7
Dependent Claim 15 words
The transistor of claim 4, wherein the collector is comprised of N type indium arsenide.
Claim 8
Dependent Claim 21 words
An integrated circuit comprising a plurality of transistors as recited in claim 2, which are epitaxially grown on a semiconductor substrate.

References Cited (Backward Citations)

US3209215A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1985-04-19 1985-10-19 1986-04-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1989-04-19 1989-10-19 1990-04-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1993-04-19 1993-10-19 1994-04-20 $7700.00 Window Closed / Lapsed

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