Correcting circuit for differential pick-up, comprising digital means

Claim 2

In a circuit for automatically correcting an electric signal given by a differential pick-up likely to have a slight unbalance, said signal having a given frequency and containing a portion resulting from such unbalance, means for determining said portion and subtracting it from the signal given by said pick-up, said means comprising: (a) a band-pass filter centered to said given frequency, followed by an adjustable gain amplifier; (b) an analyzer fed by a reference voltage at said frequency and by a voltage in phase-quadrature and by the voltage delivered by said band-pass filter, said analyzer comprising a sampler fed by said reference signal and by said signal in phase-quadrature, said sampler having two outputs and two low-pass filters connected to said two outputs, said analyzer delivering two DC-voltages X and Y proportional to the two components of the voltage delivered by said band-pass filter which are respectively in phase and in phase-quadrature with respect to said reference-voltage; (c) a first stage comprising: a threshold comparator fed by voltage X; a counter-back counter connected to said comparator; a clock for feeding said counter-back counter; a digital-analog converter connected to said counter; a multiplier with two inlets and one outlet, one of said inlets being fed by said reference voltage, while the other is connected to said converter; (d) a second stage comprising: a threshold comparator fed by voltage Y; a counter-back counter connected to said comparator; a clock for feeding said counter-back counter, a digital-analog converter connected to said counter-back counter; a multiplier with two inlets and one outlet, one of said inlets being fed by said voltage in phase-quadrature with respect to said reference-voltage, while the other inlet is connected to said converter; (e) an adder with two inlets and one outlet, one of said inlets being connected to the first stage multiplier outlet, while the other inlet is connected to the second stage multiplier outlet, the outlet of said adder being connected to the circuit inlet by mans of a phase inverter in common for all said channels.

Claim 3

In a circuit for automatically correcting an electric signal given by a differential pick-up likely to have a slight unbalance, said signal having a given frequency and containing a portion resulting from such unbalance, means for determining said portion and subtracting it from the signal given by said pick-up, said means comprising: (a) a band-pass filter centered to said given frequency followed by an adjustable gain amplifier; (b) an analyzer fed by a reference voltage at said frequency and by a voltage in phase-quadrature and by the voltage delivered by said band-pass filter, said analyzer comprising a sampler fed by said reference signal and by said signal in phase-quadrature, said sampler having two outputs and two low-pass filters connected to said two outputs, said analyzer delivering two DC-voltages X and Y proportional to the two components of the voltage delivered by said band-pass filter which are respectively in phase and in phase-quadrature with respect to said reference-voltage; (c) a first stage comprising: a threshold comparator fed by voltage X, a counter-back counter connected to said comparator; a clock for feeding said counter-back counter; a digital-analog converter connected to said counter; a multiplier with two inlets and one outlet, one of said inlets being fed by said reference voltage, while the other is connected to said converter; (d) a second stage comprising: a threshold comparator fed by voltage Y; a counter-back counter connected to said comparator; a clock for feeding said counter-back counter, a digital-analog converter connected to said counter-back counter; a multiplier with two inlets and one outlet, one of said inlets being fed by said voltage in phase-quadrature with respect to said reference-voltage, while the other inlet is connected to said converter; (e) an adder with two inlets and one outlet, one of said inlets being connected to the first stage multiplier outlet, while the other inlet is connected to the second stage multiplier outlet, the outlet of said adder being connected to the circuit inlet by means of a phase inverter in common for all said channels; (f) means for controlling the gain of said adjustable gain amplifier at a maximum value and at a minimum value and at a value depending on the voltage at the outlet thereof, said means comprising a peak pick-up connected to the circuit inlet, a comparator connected to said pick-up, a monostable flip-flop circuit, a logical gate with two inlets and one outlet, connected to a circuit for automatically controlling the gain of said amplifier, a logical gate of the AND-type with three inlets, one of which is connected to said circuit for controlling the gain while the other two are connected to the outlets of said threshold comparator circuits, a single AND-gate with as many inlets as there are channels, said inlets being connected to said AND-gates with three inlets belonging to each of said channels, a monostable circuit connected to said single AND-gate, and a bistable flip-flop provided with a resetting inlet and two extra outlets, one of which is connected to said circuit for automatically controlling the gain, while the other is connected to said logical gate with two inlets.

Claim 4

In a circuit for automatically correcting an electric signal given by a differential pick-up likely to have a slight unbalance, said signal having a given frequency and containing a portion resulting from such unbalance, means for determining said portion and subtracting it from the signal given by said pick-up, said means comprising: (a) a band-pass filter centered to said given frequency followed by an adjustable gain amplifier; (b) an analyzer fed by a reference voltage at said frequency and by a voltage in phase-quadrature and by the voltage delivered by said band-pass filter, said analyzer comprising a sampler fed by said reference signal and by said signal in phase-quadrature, said sampler having two outputs and two low-pass filters connected to said two outputs, said analyzer delivering two DC-voltages X and Y proportional to the two components of the voltage delivered by said band-pass filter which are respectively in phase and in phase-quadrature with respect to said reference-voltage; (c) a first stage comprising: a threshold comparator fed by voltage X, a counter-back counter connected to said comparator; a clock for feeding said counter-back counter; a digital-analog converter connected to said counter; a multiplier with two inlets and one outlet, one of said inlets being fed by said reference voltage, while the other is connected to said converter; (d) a second stage comprising: a threshold comparator fed by voltage Y; a counter-back counter connected to said comparator; a clock for feeding said counter-back counter, a digital-analog converter connected to said counter-back counter; a multiplier with two inlets and one outlet, one of said inlets being fed by said voltage in phase-quadrature with respect to said reference-voltage, while the other inlet is connected to said converter; (e) an adder with two inlets and one outlet, one of said inlets being connected to the first stage multiplier outlet, while the other inlet is connected to the second stage multiplier outlet, the outlet of said adder being connected to the circuit inlet by means of a phase inverter in common for all said channels; (f) means for controlling the gain of said adjustable gain amplifier at a maximum value and at a minimum value and at a value depending on the voltage at the outlet thereof, said means comprising a peak pick-up connected to the circuit inlet, a comparator connected to said pick-up, a monostable flip-flop circuit, a logical gate with two inlets and one outlet, connected to a circuit for automatically controlling the gain of said amplifier, a logical gate of the AND-type with three inlets, one of which is connected to said circuit for controlling the gain while the other two are connected to the outlets of said threshold comparator circuits, a single AND-gate with as many inlets as there are channels, said inlets being connected to said AND-gates with three inlets belonging to each of said channels, a monostable circuit connected to said single AND-gate, and a bistable flip-flop provided with a resetting inlet and two extra outlets, one of which is connected to said circuit for automatically controlling the gain, while the other is connected to said logical gate with two inlets.