US4323970A
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US
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Method and circuit arrangement for generating setting signals for signal generators of a traffic signal system, particularly a street traffic signal system
Assignee: Siemens AG
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Filing: 1980-06-02
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Granted: 1982-04-06
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Expires: 2000-06-02
Abstract
Abstract A method and a circuit arrangement for generating setting signals for signal generators of a traffic signal system, particularly of a street traffic signal system, upon employment of indications of time intervals between mutually hostile traffic flows contained in a time interval matrix are discussed. The time intervals are read from the time interval matrix for each entry signal group and subtracted from the greatest time interval value which greatest time interval value is reduced in value in cyclical succession. When this value is reduced to zero or, respectively, when a zero difference is determined in the course of the difference formations, then appropriate setting signals for the signal generators of the traffic signal system are emitted. In another embodiment provides that the time intervals of entry signal groups selected as being non-determinant for influencing a change of signal are first retained unchanged by a separate marking and are only made effective for reduction of their value in that case in which the non-marked entry time intervals of the entry signal groups hostile to the same clearing signal groups have elapsed. These techniques effect a controlled stoppage and initiation of traffic flow in accordance with specific intersection plans in a simple and precise manner.
Inventors
- 👤 Heinrich Brunner
- 👤 Karin Fischer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:29
CPC Classifications
G; G08; G08G; G08G1/00; G08G1/097
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
196 words
A method for generating setting signals for operating traffic signal generators which control mutually hostile traffic flows, comprising the steps of: storing in a matrix memory time intervals corresponding to entry signal groups representing release of traffic flow by respective traffic signal generators and associated to hostile clearing signal groups representing stoppage of traffic flow by respective traffic signal generators; reading the time intervals corresponding to a distinct entry signal group and associated to clearing signal groups hostile to said entry signal group from the matrix memory; storing the greatest time interval of said time intervals read from the matrix memory in a separate storage element and cyclically reducing said stored time interval to zero; subtracting each of said time intervals read from the matrix memory from said stored greatest time interval being cyclically reduced; detecting a zero difference of the subtraction results and emitting a respective block signal for a signal generator of the appertaining clearing signal group to which the respective subtracted time interval is associated; and emitting a release signal to a signal generator of said distinct entry signal group upon detection of a zero value of said cyclically reduced greatest time interval.
Claim 2
Independent Claim
196 words
A method for generating setting signals for operating traffic signal generators which control mutually hostile traffic flows, comprising the steps of: storing in a matrix memory time intervals corresponding to entry signal groups representing release of traffic flow by respective traffic signal generators and associated to hostile clearing signal groups representing stoppage of traffic flow by respective traffic signal generators; reading the time intervals corresponding to a distinct entry signal group and associated to clearing signal groups hostile to said entry signal group from the matrix memory; storing the greatest time interval of said time intervals read from the matrix memory in a separate storage element and cyclically reducing said stored time interval to zero; subtracting each of said time intervals read from the matrix memory from said stored greatest time interval being cyclically reduced; detecting a zero difference of the subtraction results and emitting a respective block signal for a signal generator of the appertaining clearing signal group to which the respective subtracted time interval is associated; and emitting a release signal to a signal generator of said distinct entry signal group upon detection of a zero value of said cyclically reduced greatest time interval.
Claim 3
Dependent Claim
40 words
The method of claim 1, wherein the step of cyclically reducing the stored greatest time interval is further defined as: reducing the stored greatest time interval by one second at each cycle, the cycle having a rhythm of one second.
Claim 4
Dependent Claim
81 words
The method of claim 1, comprising the further steps of: storing at least one of said time intervals corresponding to a distinct entry signal group representing selected information in a separate storage element; cyclically reducing said time interval representing selected information to zero after at least one of said zero differences is detected; and emitting a release signal to release the traffic flow controlled by the appertaining signal generator when said time interval representing selected information has been reduced to zero.
Claim 5
Dependent Claim
30 words
The metod of claim 3, wherein the step of storing is further defined as: storing the greatest time interval, of those time intervals representing selected information, for reduction to zero.
Claim 6
Dependent Claim
36 words
The method of claim 4, wherein each of the steps of cyclically reducing the time intervals is further defined as: cyclically reducing by one second at each cycle, the cycle having a rhythm of one second.
Claim 7
Dependent Claim
184 words
A circuit arrangement for generating setting signals for operating traffic signal generators which control mutually hostile traffic flows, comprising: a matrix memory storing time intervals corresponding to entry signal groups and associated to clearing signal groups; interrogation means connected to said matrix memory for reading respectively the time intervals corresponding to one of the entry signal groups and associated to all clearing signal groups hostile thereto; register means connected to said interrogation means for storing the read time intervals; storage means connected to said interrogation means for separately storing the greatest time interval read from said matrix memory; reduction means connected to said storage means for cyclically reducing the value of the greatest time interval read; subtraction means connected to said register means and to said storage means for subtracting the time intervals stored in said register means from the greatest time interval being cyclically reduced to form respective difference values; and evaluation means connected to said subtraction means and to said signal generators for determining when each difference value reaches zero and responsive thereto to emit output signals for controlling the signal generators.
Claim 8
Dependent Claim
184 words
A circuit arrangement for generating setting signals for operating traffic signal generators which control mutually hostile traffic flows, comprising: a matrix memory storing time intervals corresponding to entry signal groups and associated to clearing signal groups; interrogation means connected to said matrix memory for reading respectively the time intervals corresponding to one of the entry signal groups and associated to all clearing signal groups hostile thereto; register means connected to said interrogation means for storing the read time intervals; storage means connected to said interrogation means for separately storing the greatest time interval read from said matrix memory; reduction means connected to said storage means for cyclically reducing the value of the greatest time interval read; subtraction means connected to said register means and to said storage means for subtracting the time intervals stored in said register means from the greatest time interval being cyclically reduced to form respective difference values; and evaluation means connected to said subtraction means and to said signal generators for determining when each difference value reaches zero and responsive thereto to emit output signals for controlling the signal generators.
Claim 9
Dependent Claim
103 words
The circuit arrangement of claim 6, and further comprising: a control device operable to produce control pulses; and wherein said interrogation means comprises first and second interrogation circuits connected to said matrix memory for reading time intervals; a first counter operated by said control device and connected to said first interrogation circuit and operable to sequentially control said interrogation circuit to read entry signal group information; and a second counter operated by said control device and connected to said second interrogation circuit and operable to sequentially control said second interrogation circuit to read clearing group information hostile to the respective entry signal group.
Claim 10
Dependent Claim
124 words
The circuit arrangement of claim 6, and further comprising: a separate register including an information input connected to said interrogation means for receiving time interval information as selected information, and including an input connected to said reduction means for reducing cyclically the stored time interval information; a logic circuit connected between said evaluation means and said input connected to said reduction means and operable to gate through said input in response to at least one of said evaluation means emitting an output signal associated to a zero difference; and additional evaluation means connected to said separate register and to an additional signal generator and operable in response to the selected information reaching zero to emit an output signal to control the respective signal generator.
Claim 11
Dependent Claim
88 words
The circuit arrangement of claim 8, wherein: said evaluation means comprises a plurality of evaluation circuits each assigned to a respective traffic signal generator; and said logic circuit comprises a first AND gate having inputs connected to selected ones of said evaluation circuits, and an output, and a second AND gate having an output connected to said input of said separate register connected to said reduction means, a first input connected to said output of said first AND gate and a second input connected to said reduction means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-05 | 1985-10-05 | 1986-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-05 | 1989-10-05 | 1990-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-05 | 1993-10-05 | 1994-04-06 | $7700.00 | Window Closed / Lapsed |