US4322831A
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Programmed digital secondary clock
Assignee: Simplex Time Recorder Co
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Filing: 1978-06-06
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Granted: 1982-03-30
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Expires: 1998-06-06
Abstract
Abstract A programmed digital secondary clock which functions as a master clock, a sub-master clock or a slave clock. The master clock maintains an updated real time count based on a 50 hz or 60 hz ac line or digital oscillator signal, displays the count, and serially transmits digital information representative of the updated real time count for use by a slave clock. The sub-master clock, receives an hourly or twice-a-day correction signal from a conventional master clock or a conventional electronic receiver, corrects the real time count, displays the corrected count, and serially transmits digital information representative of the corrected real time count for use by a slave clock. Identical programmed digital secondary clocks can be connected in daisy chain. The first clock can operate as a master clock or as a sub-master clock. The following clocks can be operated as slave clocks. The slave clock, receives serial digital information representative of real time every second, maintains an updated real time count based on the received information, displays the count, and serially transmits digital information representative of the real time count for use by a following slave clock. The programmed digital secondary clock can be operated as an elapsed timer or as an interval timer without interfering with the operation of the clock as a master, sub-master or slave clock.
Inventors
- 👤 Ronald H. Peterson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:17
CPC Classifications
G; G04; G04G; G04G9/00; G04G9/0005; G04G9/0011; G04G7/00
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
184 words
A programmed digital secondary clock, comprising: real time counting means adapted for selective connection to a reference frequency line carrying a reference frequency signal for maintaining a count of real time based on the reference frequency signal, serial data transmitting means adapted for connection to a slave secondary clock for transmitting the real time count maintained in said real time counting means to the slave secondary clock in serial data format at said reference frequency, display means for numerically displaying the real time count maintained by said real time counting means, serial data receiving means adapted to receive a real time count in serial data format, means for updating the real time count maintained by said real time counting means with the real time count received in serial data format, and correction means adapted for selective connection to a master clock or to an electronic receiver for correcting the real time count maintained by said real time counting means in response to the width of a correction pulse signal produced by said master clock or a correction signal produced by said electric clock receiver.
Claim 2
Dependent Claim
184 words
A programmed digital secondary clock, comprising: real time counting means adapted for selective connection to a reference frequency line carrying a reference frequency signal for maintaining a count of real time based on the reference frequency signal, serial data transmitting means adapted for connection to a slave secondary clock for transmitting the real time count maintained in said real time counting means to the slave secondary clock in serial data format at said reference frequency, display means for numerically displaying the real time count maintained by said real time counting means, serial data receiving means adapted to receive a real time count in serial data format, means for updating the real time count maintained by said real time counting means with the real time count received in serial data format, and correction means adapted for selective connection to a master clock or to an electronic receiver for correcting the real time count maintained by said real time counting means in response to the width of a correction pulse signal produced by said master clock or a correction signal produced by said electric clock receiver.
Claim 3
Dependent Claim
49 words
The programmed digital secondary clock according to claim 1 including means for selectively maintaining an incremented count of elapsed time, means for selectively interrupting the elapsed time count, means for selectively resuming said elapsed time count, and means for causing said numerical display to display said elapsed time count.
Claim 4
Dependent Claim
60 words
The programmed digital secondary clock according to claim 1 including means for selectively maintaining a decremented count of interval time, means for selectively presetting said count of interval time, means for selectively interrupting said count of interval time, means for selectively resuming said count of interval time, and means for causing said numerical display means to display said interval count.
Claim 5
Dependent Claim
22 words
The programmed digital secondary clock according to claim 2 including means for indicating that said decremented count of interval time is zero.
Claim 6
Dependent Claim
89 words
The programmed digital secondary clock according to claim 1 including detecting means for detecting the presence or absence of said real time count in serial data format received by said serial data receiving means, oscillator means for generating a reference frequency digital pulse train, and means for causing said real time counting means to maintain a count of real time based on said reference frequency pulse train if said detecting means detects the absence of said real time count in serial data format for a preselected interval of time.
Claim 7
Dependent Claim
192 words
A programmed digital secondary clock, comprising: a real time register for maintaining a count of real time based on a reference frequency signal, said real time register having a stage for maintaining a count of units of seconds based on said reference frequency signal, a buffer register operatively associated with said real time register, means for detecting a change in said units of seconds count maintained by said real time register, means for loading said real time count in said buffer register when said change in said units of seconds count is detected, means for serially shifting said loaded real time count out of said buffer register at said reference frequency to a slave secondary clock, means for numerically displaying said real time count maintained by said real time register, means for receiving a real time count in serial data format at said reference frequency, means for loading said real time count received in serial data format into said buffer register at said reference frequency, and means for transferring said real time count loaded into said buffer register to said real time register at a frequency of at least once each second.
Claim 8
Dependent Claim
192 words
A programmed digital secondary clock, comprising: a real time register for maintaining a count of real time based on a reference frequency signal, said real time register having a stage for maintaining a count of units of seconds based on said reference frequency signal, a buffer register operatively associated with said real time register, means for detecting a change in said units of seconds count maintained by said real time register, means for loading said real time count in said buffer register when said change in said units of seconds count is detected, means for serially shifting said loaded real time count out of said buffer register at said reference frequency to a slave secondary clock, means for numerically displaying said real time count maintained by said real time register, means for receiving a real time count in serial data format at said reference frequency, means for loading said real time count received in serial data format into said buffer register at said reference frequency, and means for transferring said real time count loaded into said buffer register to said real time register at a frequency of at least once each second.
Claim 9
Dependent Claim
56 words
The programmed digital secondary clock according to claim 6 including means adapted for selective connection to a master clock or to an electronic receiver for correcting the real time count maintained in said real time register in response to a correction signal produced by said master clock or a correction signal produced by said electronic receiver.
Claim 10
Dependent Claim
59 words
The programmed digital secondary clock according to claim 6 including an elapsed time register for selectively maintaining an incremented count of elapsed time based on said reference frequency signal, means for selectively interrupting the elapsed time count, means for selectively resuming said elapsed time count, and means for causing said numerical display means to display said elapsed time count.
Claim 11
Dependent Claim
64 words
The programmed digital secondary clock according to claim 6 including a time register for maintaining a decremented count of interval time, means for selectively presetting said time register, means for selectively interrupting said decremented count of interval time, means for selectively resuming said decremented count of interval time, and means for causing said numerical display means to display said decremented count of interval time.
Claim 12
Dependent Claim
21 words
The programmed digital secondary clock according to claim 9 including means for indicating that said count of interval time is zero.
Claim 13
Dependent Claim
238 words
A programmed digital secondary clock, comprising: a real time register for maintaining a count of real time based on a reference frequency signal, said real time register having a stage for maintaining a count of units of seconds based on said reference frequency signal, a buffer register operatively associated with said real time register, means for detecting a change in said real time count maintained by said real time register, means for loading said real time count in said buffer register when said change in said units of seconds count is detected, means for serially shifting said loaded real time count out of said buffer register at said reference frequency to a slave secondary clock, means for numerically displaying said real time count maintained by said real time register, means adapted for selective connection to a master clock or to an electronic receiver for periodically correcting the real time count maintained in said real time register in response to a correction signal produced by said master clock or a correction signal produced by said electronic receiver, means for receiving a real time count at said reference frequency in serial data format, means for loading said real time count received in serial data format into said buffer register at said reference frequency, and means for transferring said real time count loaded into said buffer register to said real time register at a frequency of at least once each second.
Claim 14
Dependent Claim
238 words
A programmed digital secondary clock, comprising: a real time register for maintaining a count of real time based on a reference frequency signal, said real time register having a stage for maintaining a count of units of seconds based on said reference frequency signal, a buffer register operatively associated with said real time register, means for detecting a change in said real time count maintained by said real time register, means for loading said real time count in said buffer register when said change in said units of seconds count is detected, means for serially shifting said loaded real time count out of said buffer register at said reference frequency to a slave secondary clock, means for numerically displaying said real time count maintained by said real time register, means adapted for selective connection to a master clock or to an electronic receiver for periodically correcting the real time count maintained in said real time register in response to a correction signal produced by said master clock or a correction signal produced by said electronic receiver, means for receiving a real time count at said reference frequency in serial data format, means for loading said real time count received in serial data format into said buffer register at said reference frequency, and means for transferring said real time count loaded into said buffer register to said real time register at a frequency of at least once each second.
Claim 15
Dependent Claim
86 words
The programmed digital secondary clock according to claim 1, 8 or 11 including detecting means for detecting the presence or absence of said received real time count in serial data format, oscillator means for generating a reference frequency digital pulse train, and means for causing said real time counting means to maintain a count of real time based on said reference frequency pulse train if said detecting means detects the absence of said real time count in serial data format for a preselected interval of time.
Claim 16
Dependent Claim
49 words
The programmed digital secondary clock according to claim 11 including means for selectively maintaining an incremented count of elapsed time, means for selectively interrupting the elapsed time count, means for selectively resuming said elapsed time count, and means for causing said numerical display to display said elapsed time count.
Claim 17
Dependent Claim
60 words
The programmed digital secondary clock according to claim 11 including means for selectively maintaining a decremented count of interval time, means for selectively presetting said count of interval time, means for selectively interrupting said count of interval time, means for selectively resuming said count of interval time, and means for causing said numerical display means to display said interval count.
Claim 18
Dependent Claim
22 words
The programmed digital secondary clock according to claim 14 including means for indicating that said decremented count of interval time is zero.
Claim 19
Dependent Claim
167 words
The programmed digital secondary clock, comprising: real time counting means adapted for selective connection to a reference frequency line carrying a reference frequency signal for maintaining a count of real time based on the reference frequency signal, serial data transmitting means adapted for connection to a slave secondary clock for transmitting the real time count maintained in said real time counting means to the slave secondary clock in serial data format at said reference frequency, display means for numerically displaying the real time count maintained by said real time counting means, and correction means adapted for selective connection to a master clock or to an electronic receiver for correcting the real time count maintained by said real time counting means in response to a correction pulse signal produced by said master clock or by said electronic receiver, including means for detecting the pulse width of said correction pulse signal and for correcting the real time count depending on the detected pulse width of said correction pulse signal.
Claim 20
Dependent Claim
167 words
The programmed digital secondary clock, comprising: real time counting means adapted for selective connection to a reference frequency line carrying a reference frequency signal for maintaining a count of real time based on the reference frequency signal, serial data transmitting means adapted for connection to a slave secondary clock for transmitting the real time count maintained in said real time counting means to the slave secondary clock in serial data format at said reference frequency, display means for numerically displaying the real time count maintained by said real time counting means, and correction means adapted for selective connection to a master clock or to an electronic receiver for correcting the real time count maintained by said real time counting means in response to a correction pulse signal produced by said master clock or by said electronic receiver, including means for detecting the pulse width of said correction pulse signal and for correcting the real time count depending on the detected pulse width of said correction pulse signal.
Claim 21
Dependent Claim
203 words
A programmed digital secondary clock, comprising: a real time register for maintaining a count of real time based on a reference frequency signal, said real time register having a stage for maintaining a count of units of seconds based on said reference frequency signal, a buffer register operatively associated with said real time register, means for detecting a change in said units of seconds count maintained by said real time register, means for loading said real time count in said buffer register when said change in said units of seconds count is detected, means for serially shifting said loaded real time count out of said buffer register at said reference frequency to a slave secondary clock, means for numerically displaying said real time count maintained by said real time register, means adapted for selective connection to a master clock or to an electronic receiver for correcting the real time count maintained in said real time register in response to a correction pulse signal produced by said master clock or by said electronic receiver, including means for detecting the pulse width of said correction pulse signal and for correcting the real time count depending on the detected pulse width of said correction pulse signal.
Claim 22
Dependent Claim
203 words
A programmed digital secondary clock, comprising: a real time register for maintaining a count of real time based on a reference frequency signal, said real time register having a stage for maintaining a count of units of seconds based on said reference frequency signal, a buffer register operatively associated with said real time register, means for detecting a change in said units of seconds count maintained by said real time register, means for loading said real time count in said buffer register when said change in said units of seconds count is detected, means for serially shifting said loaded real time count out of said buffer register at said reference frequency to a slave secondary clock, means for numerically displaying said real time count maintained by said real time register, means adapted for selective connection to a master clock or to an electronic receiver for correcting the real time count maintained in said real time register in response to a correction pulse signal produced by said master clock or by said electronic receiver, including means for detecting the pulse width of said correction pulse signal and for correcting the real time count depending on the detected pulse width of said correction pulse signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-03-29 | 1985-09-28 | 1986-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-03-29 | 1989-09-28 | 1990-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-03-29 | 1993-09-28 | 1994-03-30 | $7700.00 | Window Closed / Lapsed |