US4317167A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for the processing of information
Assignee: Ruhrtal Elektrizitatsgesellschaft Hartig GmbH and Co
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Filing: 1979-09-20
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Granted: 1982-02-23
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Expires: 1999-09-20
Abstract
Abstract A circuit arrangement in which an information processor which includes at least one microprocessor, especially a microprocessor responding to measurement, control or regulatory signals in an energy supply installation, an industrial plant or process or the like, is monitored by a control unit which responds upon a failure of the microprocessor to provide a failure signal which can be used to alert an operator.
Inventors
- 👤 Alfred Hartig
- 👤 Harald Beckermann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:03
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/30; G06F11/32; G06F11/324; G06F11/327
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
139 words
An information-processing circuit comprising, in combination: a microprocessor-controlled unit responsive to input signals of an installation representing parameters of the operation thereof to be monitored and producing output signals for controlling said operation, said microprocessor-controlled unit including a microprocessor having a power supply source and a memory cooperating with said microprocessor; and a control unit connected to said microprocessor for continuously monitoring the operation thereof, said control unit being responsive to a control signal outputted from said microprocessor and including means for generating a failure signal upon detection of a functional failure of said microprocessor, said microprocessor outputting a train of control signals in predetermined time-spaced relationship which pass through at least one stage of the microprocessor prior to appearing at a control terminal thereof, said control unit being responsive to a failure in the train of control signals.
Claim 2
Dependent Claim
139 words
An information-processing circuit comprising, in combination: a microprocessor-controlled unit responsive to input signals of an installation representing parameters of the operation thereof to be monitored and producing output signals for controlling said operation, said microprocessor-controlled unit including a microprocessor having a power supply source and a memory cooperating with said microprocessor; and a control unit connected to said microprocessor for continuously monitoring the operation thereof, said control unit being responsive to a control signal outputted from said microprocessor and including means for generating a failure signal upon detection of a functional failure of said microprocessor, said microprocessor outputting a train of control signals in predetermined time-spaced relationship which pass through at least one stage of the microprocessor prior to appearing at a control terminal thereof, said control unit being responsive to a failure in the train of control signals.
Claim 3
Dependent Claim
27 words
The information-processing circuit defined in claim 1 wherein said control unit includes a time constant network responsive to an excessive duration between control signals at said terminal.
Claim 4
Dependent Claim
16 words
The information-processing circuit defined in claim 2 wherein said time constant network is a resistor-capacitor network.
Claim 5
Dependent Claim
16 words
The information-processing circuit defined in claim 1 wherein said control unit forms part of the microprocessor.
Claim 6
Dependent Claim
21 words
The information-processing circuit defined in claim 4 wherein the microprocessor has a self-monitoring output terminal at which said failure signal appears.
Claim 7
Dependent Claim
24 words
The information-processing circuit defined in claim 1, further comprising an optoacoustic output device triggered by said failure signal and connected to said control unit.
Claim 8
Dependent Claim
16 words
The information-processing circuit defined in claim 1 wherein said failure signal is an electronic alarm signal.
Claim 9
Dependent Claim
40 words
The information-processing circuit defined in claim 1, further comprising a standby microprocessor operatively connected to said control unit and switched into said circuit upon the generation of said failure signal by said control unit in place of the first-mentioned microprocessor.
Claim 10
Dependent Claim
26 words
The information processing circuit defined in claim 1, further comprising an electric power supply for said control unit independent of the supply for said microprocessor-controlled unit.
Claim 11
Independent Claim
156 words
A method of operating a microprocessor for the control of an electric pkower or other industrial installation which comprises the steps of: detecting a multiplicity of operating conditions at said installation and producing respective electrical input signals representing parameters of said operating conditions; applying said input signals to a preprogrammed microprocessor and generating a multiplicity of output signals representing preprogrammed relationships between the input signals and operational instructions to be commanded by said output signals; controlling operating parameters of said installation with said output signals; permanently monitoring the function of said microprocessor and generating a failure signal upon the functional failure thereof by generating within said microprocessor a train of control signals in predetermined time-spaced relationship which pass through at least one stage of the microprocessor before being outputted and detecting a failure of an outputted control signal of said train to generate said failure signal; and generating an alarm in response to said failure signal.
Claim 12
Independent Claim
156 words
A method of operating a microprocessor for the control of an electric pkower or other industrial installation which comprises the steps of: detecting a multiplicity of operating conditions at said installation and producing respective electrical input signals representing parameters of said operating conditions; applying said input signals to a preprogrammed microprocessor and generating a multiplicity of output signals representing preprogrammed relationships between the input signals and operational instructions to be commanded by said output signals; controlling operating parameters of said installation with said output signals; permanently monitoring the function of said microprocessor and generating a failure signal upon the functional failure thereof by generating within said microprocessor a train of control signals in predetermined time-spaced relationship which pass through at least one stage of the microprocessor before being outputted and detecting a failure of an outputted control signal of said train to generate said failure signal; and generating an alarm in response to said failure signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-02-22 | 1985-08-24 | 1986-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-02-22 | 1989-08-24 | 1990-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-02-22 | 1993-08-24 | 1994-02-23 | $7700.00 | Window Closed / Lapsed |