US4314288A
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US
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Amplitude and phase equalizer
Assignee: Ampex Corp
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Filing: 1980-08-29
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Granted: 1982-02-02
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Expires: 2000-08-29
Abstract
Abstract Minimal realization of an optimum amplitude and phase equalizer is disclosed. A first amplifier circuit including first respective passive filter elements provides both high and low frequency amplitude equalization. A second amplifier circuit including second respective passive filter elements provides first, second or higher order phase equalization, respectively, with gain. The equalizer operates between voltage sources and virtual ground to minimize noise picked up from parasitic capacities and external sources.
Inventors
- 👤 Maung Gyi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:33
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/02; G11B5/027; G11B5/035; H; H04; H04B; H04B3/00; H04B3/02; H04B3/04; H04B3/14; H04B3/143; H04B3/144
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
298 words
An amplitude and phase equalization circuit, comprising in combination: an input terminal for receiving an input signal to be amplitude and phase equalized within a given frequency band; a first amplifier means having an inverting input, a non-inverting input coupled to ground, and an output for providing an amplitude equalized output signal; a first passive filter means coupled between said input terminal and said inverting input of said first amplifier means to provide an increasing amplitude characteristic with frequency at said output of the first amplifier means within a known high frequency portion of said given frequency band; a second passive filter means coupled between said output and inverting input of said first amplifier means to provide a decreasing amplitude characteristic with frequency at said output of the first amplifier means within a known low frequency portion of said given frequency band, said amplitude equalized output signal obtained at said output of the first amplifier means having a non-linear phase characteristic with frequency within said given frequency band; a second amplifier means having an inverting and a non-inverting input, respectively, and an output, an input impedance coupled between said output of said first amplifier means and said inverting input of the second amplifier means, a feedback impedance coupled between said output of the second amplifier means and its inverting input; and a third passive filter means of a selected order coupled between said output of the first amplifier means, said non-inverting input of the second amplifier means and ground, respectively, to provide at said output of the second amplifier means an amplitude and phase equalized output signal having a substantially linearly increased amplitude with respect to said output signal of said first amplifier means and having a substantially linear phase characteristic with frequency within said given frequency band.
Claim 2
Dependent Claim
298 words
An amplitude and phase equalization circuit, comprising in combination: an input terminal for receiving an input signal to be amplitude and phase equalized within a given frequency band; a first amplifier means having an inverting input, a non-inverting input coupled to ground, and an output for providing an amplitude equalized output signal; a first passive filter means coupled between said input terminal and said inverting input of said first amplifier means to provide an increasing amplitude characteristic with frequency at said output of the first amplifier means within a known high frequency portion of said given frequency band; a second passive filter means coupled between said output and inverting input of said first amplifier means to provide a decreasing amplitude characteristic with frequency at said output of the first amplifier means within a known low frequency portion of said given frequency band, said amplitude equalized output signal obtained at said output of the first amplifier means having a non-linear phase characteristic with frequency within said given frequency band; a second amplifier means having an inverting and a non-inverting input, respectively, and an output, an input impedance coupled between said output of said first amplifier means and said inverting input of the second amplifier means, a feedback impedance coupled between said output of the second amplifier means and its inverting input; and a third passive filter means of a selected order coupled between said output of the first amplifier means, said non-inverting input of the second amplifier means and ground, respectively, to provide at said output of the second amplifier means an amplitude and phase equalized output signal having a substantially linearly increased amplitude with respect to said output signal of said first amplifier means and having a substantially linear phase characteristic with frequency within said given frequency band.
Claim 3
Dependent Claim
66 words
The amplitude and phase equalization circuit of claim 1, wherein: said first passive filter means comprises a first series combination of a capacitor, inductor and resistor, said first series combination being coupled in parallel with first resistor; and said second passive filter means comprises a second series combination of a resistor and a capacitor, said second series combination being connected in parallel with a second resistor.
Claim 4
Dependent Claim
49 words
The amplitude and phase equalization circuit of claim 2 wherein said inductor of said first series combination has resistive losses of a known value and wherein the resistance value of said resistor of said first series combination is decreased by that known value to compensate for said resistive losses.
Claim 5
Dependent Claim
36 words
The amplitude and phase equalization circuit of claim 2 further comprising a first capacitor connected in parallel with said resistor of said second series combination and a second capacitor connected in parallel with said second resistor.
Claim 6
Dependent Claim
55 words
The amplitude and phase equalization circuit of claim 2 or 3, wherein said third passive filter means comprises a third resistor coupled between said output of the first amplifier means and said non-inverting input of the second amplifier means and a third capacitor coupled between said non-inverting input of the second amplifier means and ground.
Claim 7
Dependent Claim
73 words
The amplitude and phase equalization circuit of claim 2 or 3, wherein said third passive filter means comprises a third series combination of an inductor, resistor and capacitor, said third series combination being coupled between said output of the first amplifier means and said non-inverting input of the second amplifier means, said third passive filter means further comprising a fourth resistor coupled between said non-inverting input of the second amplifier means and ground.
Claim 8
Dependent Claim
45 words
The amplitude and phase equalization circuit of claim 6, wherein said inductor of said third series combination has resistive losses of a known value and wherein the resistance value of said resistor of said third series combination is adjusted to compensate for said resistive losses.
Claim 9
Dependent Claim
111 words
The amplitude and phase equalization circuit of claim 1 for use in magnetic recording/playback devices having a plurality of selectable magnetic medium speeds, wherein; said first and second passive filter means each comprises a plurality of reactive and resistive elements, respectively, selectively connectable to said first amplifier means and wherein a said third passive filter means comprises a plurality of reactive and resistive elements selectively connectable to said second amplifier means; and means for respectively connecting selected ones of said plurality of reactive and resistive elements of said first, second and third passive filter means to said first and second amplifier means, respectively, in response to a selected magnetic medium speed.
Claim 10
Dependent Claim
132 words
The amplitude and phase equalization circuit of claim 8, wherein, said first passive filter means comprises a plurality of selectively connectable first series combinations, each comprising a capacitor, inductor and resistor, said plurality of first series combinations being connected in parallel with a first resistor; said second passive filter means comprises a plurality of selectively connectable second series combinations, each comprising a plurality of selectively connectable resistors and a capacitor said second series combinations being connected in parallel with a second resistor; and said third passive filter means comprises a plurality of third resistors selectively connectable between said output of the first amplifier means and said non-inverting input of said second amplifier means and a plurality of third capacitors selectively connectable between said non-inverting input of said second amplifier means and ground.
Claim 11
Dependent Claim
53 words
The amplitude and phase equalization circuit of claim 9 wherein said inductors of said plurality of first series combinations have respective resistive losses of known values and wherein the respective resistance values of said resistors of said first series combinations are respectively decreased by those known values to compensate for said resistive losses.
Claim 12
Dependent Claim
46 words
The amplitude and phase equalization circuit of claim 10 further comprising: a plurality of first capacitors, each capacitor connected in parallel with one of said plurality of selectively connectable resistors of said second series combinations; and a second capacitor connected in parallel with said second resistor.
Claim 13
Dependent Claim
147 words
An amplitude equalization circuit comprising in combination: an input terminal for receiving an input signal to be amplitude equalized within a given frequency band; an operational amplifier means having an inverting input, a non-inverting input coupled to ground and an output for providing an amplitude equalized output signal; a first passive filter means having an input coupled to said input terminal and having an output coupled to said inverting input of said operational amplifier means, said first passive filter means comprises a first series combination of a capacitor, inductor and resistor, said first series combination being coupled in parallel with a first resistor; and a second passive filter means coupled between said inverting input and output of said amplifier means, said second passive filter means comprises a second series combination of a resistor and capacitor, said second series combination being coupled in parallel with a second resistor.
Claim 14
Dependent Claim
147 words
An amplitude equalization circuit comprising in combination: an input terminal for receiving an input signal to be amplitude equalized within a given frequency band; an operational amplifier means having an inverting input, a non-inverting input coupled to ground and an output for providing an amplitude equalized output signal; a first passive filter means having an input coupled to said input terminal and having an output coupled to said inverting input of said operational amplifier means, said first passive filter means comprises a first series combination of a capacitor, inductor and resistor, said first series combination being coupled in parallel with a first resistor; and a second passive filter means coupled between said inverting input and output of said amplifier means, said second passive filter means comprises a second series combination of a resistor and capacitor, said second series combination being coupled in parallel with a second resistor.
Claim 15
Dependent Claim
47 words
The amplitude equalization circuit of claim 12, wherein said inductor of said first series combination has resistive losses of a known value and wherein the resistance value of said resistor of said first series combination is decreased by that known value to compensate for said resistive losses.
Claim 16
Dependent Claim
34 words
The amplitude equalization circuit of claim 12, further comprising a first capacitor connected in parallel with said resistor of said second series combination and a second capacitor connected in parallel with said second resistor.
Claim 17
Dependent Claim
139 words
A phase equalization circuit comprising in combination: an input terminal for receiving an input signal having a non-linear phase characteristic with frequency within a given frequency band; an operational amplifier means having an inverting and a non-inverting input, respectively, and an output, an input impedance coupled between said input terminal and said inverting input of said amplifier means, and a feedback impedance coupled between said inverting input and said output of said amplifier means; and a passive reactive filter means of a selected order coupled between said input terminal, said non-inverting input of said amplifier means and ground, respectively, to provide at said output of said amplifier means a phase equalized output signal having a substantially linearly increased amplitude with respect to said input signal and having a substantially linear phase characteristic with frequency within said given frequency band.
Claim 18
Dependent Claim
139 words
A phase equalization circuit comprising in combination: an input terminal for receiving an input signal having a non-linear phase characteristic with frequency within a given frequency band; an operational amplifier means having an inverting and a non-inverting input, respectively, and an output, an input impedance coupled between said input terminal and said inverting input of said amplifier means, and a feedback impedance coupled between said inverting input and said output of said amplifier means; and a passive reactive filter means of a selected order coupled between said input terminal, said non-inverting input of said amplifier means and ground, respectively, to provide at said output of said amplifier means a phase equalized output signal having a substantially linearly increased amplitude with respect to said input signal and having a substantially linear phase characteristic with frequency within said given frequency band.
Claim 19
Dependent Claim
137 words
A phase equalization circuit comprising in combination: an input terminal (90) for receiving an input signal having a non-linear phase characteristic with frequency within a given frequency band; an operational amplifier means (92) having an inverting (96) and a non-inverting input (98), respectively, and an output (95), an input impedance (94) coupled between said input terminal (90) and said inverting input (96) of said amplifier means (92), and a feedback impedance (106) coupled between said inverting input (96) and said output (95) of said amplifier means (92); and a passive reactive filter means (114) comprising a resistor (110) coupled between said input terminal (90) and said non-inverting input (98) of said amplifier means (92) and a capacitor (112) coupled between said non-inverting input (98) and ground, respectively, for providing a first order phase equalization circuit with gain.
Claim 20
Dependent Claim
137 words
A phase equalization circuit comprising in combination: an input terminal (90) for receiving an input signal having a non-linear phase characteristic with frequency within a given frequency band; an operational amplifier means (92) having an inverting (96) and a non-inverting input (98), respectively, and an output (95), an input impedance (94) coupled between said input terminal (90) and said inverting input (96) of said amplifier means (92), and a feedback impedance (106) coupled between said inverting input (96) and said output (95) of said amplifier means (92); and a passive reactive filter means (114) comprising a resistor (110) coupled between said input terminal (90) and said non-inverting input (98) of said amplifier means (92) and a capacitor (112) coupled between said non-inverting input (98) and ground, respectively, for providing a first order phase equalization circuit with gain.
Claim 21
Dependent Claim
150 words
A phase equalization circuit comprising in combination: an input terminal (90) for receiving an input signal having a non-linear phase characteristic with frequency within a given frequency band; an operational amplifier means (92) having an inverting (96) and a non-inverting input (98), respectively, and an output (95), an input impedance (94) coupled between said input terminal (90) and said inverting input (96) of said amplifier means (92), and a feedback impedance (106) coupled between said inverting input (96) and said output (95) of said amplifier means (92); and a passive reactive filter means (120) comprising a series combination of a first resistor (122), an inductor (124) and a capacitor (126), coupled between said input terminal (90) and said non-inverting input (98) of said amplifier means (92), and a second resistor (128) coupled between said non-inverting input (98) and ground, respectively, for providing a second order phase equalization circuit with gain.
Claim 22
Dependent Claim
150 words
A phase equalization circuit comprising in combination: an input terminal (90) for receiving an input signal having a non-linear phase characteristic with frequency within a given frequency band; an operational amplifier means (92) having an inverting (96) and a non-inverting input (98), respectively, and an output (95), an input impedance (94) coupled between said input terminal (90) and said inverting input (96) of said amplifier means (92), and a feedback impedance (106) coupled between said inverting input (96) and said output (95) of said amplifier means (92); and a passive reactive filter means (120) comprising a series combination of a first resistor (122), an inductor (124) and a capacitor (126), coupled between said input terminal (90) and said non-inverting input (98) of said amplifier means (92), and a second resistor (128) coupled between said non-inverting input (98) and ground, respectively, for providing a second order phase equalization circuit with gain.
Claim 23
Dependent Claim
37 words
The phase equalization circuit of claim 17, wherein said inductor (124) has resistive losses of a known value (RY) and wherein the resistance value of said first resistor (122) is adjusted to compensate for said resistive losses.
References Cited (Backward Citations)
US4110798A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-02-01 | 1985-08-03 | 1986-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-02-01 | 1989-08-03 | 1990-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-02-01 | 1993-08-03 | 1994-02-02 | $7700.00 | Window Closed / Lapsed |