Bias control for high efficiency inverter circuit

Claim 2

A push-pull inverter circuit connected to a unidirectional voltage input supply and being operable to provide an alternating voltage output, the inverter circuit having a main transformer in circuit with two alternately conducting switching transistors, each having a base, an emitter and a collector, the improvement comprising: separate non-coupled saturable inductor means for each transistor connected in circuit with the base-emitter junction thereof; and circuit means effective to establish an operating bias potential at the base of each transistor lower than the respective emitter potential whereby each saturable inductor means upon saturation provides an effective direct connection between said base and said operating bias potential for ensuring the rapid evacuation of charge carriers from the base for thereby turning the transistor off.

Claim 3

The inverter circuit of claim 1 including: positive bias means connected to said circuit means and operable to initiate conduction of one of said transistors.

Claim 4

The inverter circuit of claim 2 including: current limiting means connected in circuit with said positive bias means and operable to render said positive bias means effectively inoperative once said operating bias potential is established.

Claim 5

The inverter circuit of claim 1 wherein: said inductor means are saturable transformers.

Claim 6

The inverter circuit of claim 4 wherein: said circuit means includes a common bias conductor; and said saturable transformers each have a winding connected in circuit between said common bias conductor and a base of a transistor.

Claim 7

The inverter circuit of claim 5 wherein: said circuit means additionally includes a common reference conductor; and electrical charge storing means connected between said reference conductor and said bias conductor.

Claim 8

The inverter circuit of claim 6 wherein: said reference conductor is connected to said emitters of both transistors.

Claim 9

The inverter circuit of claim 7 including: unidirectional conductive means connected in circuit between said bases of both transistors and said reference conductor.

Claim 10

The inverter circuit of claim 8 wherein: said unidirectional conductive means includes a voltage dropping element effective in part to establish said operating bias potential.

Claim 11

The inverter circuit of claim 9 wherein: said voltage dropping element is common to said unidirectional conductive means for both said transistors.

Claim 12

The inverter circuit of claim 9 wherein: said voltage dropping element is a Zener diode.

Claim 13

The inverter circuit of claim 11 wherein: said unidirectional conductive means includes a diode connected to the base of each of said transistors; and said Zener diode is operatively and intermittently connected in series with each of said diodes.

Claim 14

The inverter circuit of claim 10 wherein: said voltage dropping element is operable to maintain said operating bias potential substantially constant during the alternate conduction of both transistors.

Claim 15

A push-pull inverter circuit connected to a unidirectional voltage input supply and being operable to provide an alternating voltage output, the inverter circuit having two alternately conducting switching transistors, each having a base, a collector and an emitter, the improvement comprising: first circuit means for connecting the transistors in series with the input supply voltage; separate non-coupled saturable inductor means for each transistor connected in circuit with the base-emitter junction thereof; and second circuit means effective to establish an operating bias potential at the base of each transistor lower than the respective emitter potential whereby each saturable inductor mean upon saturation provides an effective direct connection between said base and said operating bias potential for ensuring the rapid evacuation of charge carriers from the base for thereby turning the transistor off.

Claim 16

A push-pull inverter circuit connected to a unidirectional voltage input supply and being operable to provide an alternating voltage output, the inverter circuit having two alternately conducting switching transistors, each having a base, a collector and an emitter, the improvement comprising: first circuit means for connecting the transistors in series with the input supply voltage; separate non-coupled saturable inductor means for each transistor connected in circuit with the base-emitter junction thereof; and second circuit means effective to establish an operating bias potential at the base of each transistor lower than the respective emitter potential whereby each saturable inductor mean upon saturation provides an effective direct connection between said base and said operating bias potential for ensuring the rapid evacuation of charge carriers from the base for thereby turning the transistor off.

Claim 17

The inverter circuit of claim 14 wherein: said second circuit means includes a capacitor connected in circuit with each of said transistors and with each inductor means for maintaining the operating bias potential.

Claim 18

The inverter circuit of claim 15 wherein: said second circuit means includes unidirectional conductive means connected in circuit between the base and emitter of each transistor.

Claim 19

The inverter circuit of claim 16 including: a voltage dropping element connected in series with said unidirectional conductive means and effective in part to establish said operating bias potential.

Claim 20

The inverter circuit of claim 17 wherein: said voltage dropping element is a Zener diode.

Claim 21

A push-pull inverter circuit connected to a unidirectional voltage input supply and being operable to provide an alternating voltage output, the inverter circuit having a main transformer in circuit with two alternately conducting switching transistors, each transistor having a base, an emitter and a collector, and the inverter circuit also having a separate, non-coupled, saturable inductor for each transistor connected in circuit with the base and emitter thereof, the improvement comprising: shunt diode means in circuit with the collector and emitter of each transistor.

Claim 22

A push-pull inverter circuit connected to a unidirectional voltage input supply and being operable to provide an alternating voltage output, the inverter circuit having a main transformer in circuit with two alternately conducting switching transistors, each transistor having a base, an emitter and a collector, and the inverter circuit also having a separate, non-coupled, saturable inductor for each transistor connected in circuit with the base and emitter thereof, the improvement comprising: shunt diode means in circuit with the collector and emitter of each transistor.

Claim 23

The inverter circuit of claim 19 including: bias means effective to establish an operating bias potential at the base of each transistor lower than the respective emitter potential whereby each saturable inductor means upon saturation provides an effective direct connection between said base and said operating bias potential for ensuring the rapid evacuation of charge carriers from the base for thereby turning the transistor off.

Claim 24

A push-pull inverter circuit connected to a unidirectional voltage input supply and being operable to provide an alternating voltage output, the inverter circuit having two alternately conducting switching transistors connected in series, and each having a base, a collector and an emitter, and the inverter circuit also having a separate, non-coupled, saturable inductor for each transistor connected in circuit with the base and emitter thereof, the improvement comprising: shunt diode means in circuit with the collector and emitter of each transistor.

Claim 25

A push-pull inverter circuit connected to a unidirectional voltage input supply and being operable to provide an alternating voltage output, the inverter circuit having two alternately conducting switching transistors connected in series, and each having a base, a collector and an emitter, and the inverter circuit also having a separate, non-coupled, saturable inductor for each transistor connected in circuit with the base and emitter thereof, the improvement comprising: shunt diode means in circuit with the collector and emitter of each transistor.

Claim 26

The inverter circuit of claim 21, including: bias means effective to establish an operating bias potential at the base of each transistor lower than the respective emitter potential whereby each saturable inductor means upon saturation provides an effective direct connection between said base and said operating bias potential for ensuring the rapid evacuation of charge carriers from the base for thereby turning the transistor off.