Security communication system

Claim 1

A security communication system comprising: a transmission apparatus including a first signal generating circuit for generating a synchronizing signal, a scrambling circuit for scrambling an input information signal according to a specific code to form a scrambled information signal and for making invalid the scrambled information signal during generation of the synchronizing signal from the first signal generating circuit to insert non-signal regions into the scrambled information signals, and a signal synthesizing circuit coupled to the first signal generating circuit and the scrambling circuit for inserting the synchronizing signal from the first signal generating circuit into the non-signal regions of the scrambled information signal; a reception apparatus including a deciphering circuit for deciphering the scrambled information signal from the transmission apparatus according to a code substantially the same as said specific code, and a second signal generating circuit for detecting the synchronizing signal contained in the scrambled information signal and supplying the deciphering circuit with an output signal synchronous with the synchronizing signal to control the timing for start of a deciphering operation in the deciphering circuit; wherein said scrambling circuit has a first code generating circuit for generating said specific code in response to a synchronizing signal from said first signal generating circuit, a first inverter circuit for selectively inverting an input information signal according to the specific code from the first code generating circuit, a switching circuit which is triggered in response to a synchronizing signal from said first signal generating circuit to provide said non-signal regions in the scrambled information signal thereby preventing an output signal of said first inverter circuit from being supplied to said first signal generating circuit and a sample/hold circuit connected in series to said first inverter circuit; and wherein said first signal generating circuit has a reference signal generating circuit for supplying sampling signal to said sample/hold circuit, a first counter circuit coupled to the reference signal generating circuit for counting output signal thereof and for generating an output signal when it has count between a first predetermined count and a second predetermined count, to trigger said switching circuit, and a first synchronizing signal generator for serially generating modulation synchronizing signal, sampling clock synchronizing signal and frame synchronizing signal in response to an output signal of the first counter circuit for the duration of the output signal thereof; and said transmission apparatus further includes a balanced modulator for balance-modulating an output signal of said first signal synthesizing circuit, a second signal synthesizing circuit with one input terminal coupled to said balanced modulator, means for supplying said first signal synthesizing circuit with the sampling clock synchronizing signal and frame synchronizing signal from the first synchronizing signal generator, and means for supplying the moduation synchronizing signal from the first synchronizing signal generator to the second input terminal of the second signal synthesizing circuit.