US4304964A
Expired / Lapsed
US
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Variable frame length data converter for a speech synthesis circuit
Assignee: Texas Instruments Inc
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Filing: 1978-04-28
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Granted: 1981-12-08
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Expires: 1998-04-28
Abstract
Abstract A speech synthesis circuit is provided with a variable frame length data converter and the speech synthesizer is preferably integrated on an integrated circuit chips. The variable frame length data converter reduces the amount of data required to synthesizer human speech at a given quality level. Preferably, a full frame of data includes, a pitch parameter, an energy parameter, a repeat bit and a plurality of speech coefficients. Each parameter or coefficient has a preselected length, but each frame has a variable number of parameters or coefficients associated therewith. The parameters and coefficients are encoded and a particular code of the pitch parameter indicates that the speech is to be unvoiced. An unvoiced frame includes fewer coefficients that a voiced frame and the converter detects this particular pitch parameter and automatically sets the unsent coefficients to zero. The converter also detects the state of the repeat bit for controlling the synthesizing to use the coefficients received during the previous frame as the coefficient to be used to generate speech in response to the present frame. In this embodiment, when the repeat bit comes up, new pitch and energy parameters are inputted therewith. Further, the converters preferably detects particular codes in the energy parameter for determining when a pause occurs or when the last frame of data has been sent.
Inventors
- 👤 Richard H. Wiggins, Jr.
- 👤 George L. Brantingham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:08
CPC Classifications
G; G10; G10L; G10L19/00; G09; G09B; G09B7/00; G09B7/02; G09B7/04; G10L13/00; G10L13/08
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
189 words
A method of decoding encoded variable frame length data being coupled to a speech synthesis circuit from a memory means storing said encoded variable frame length data, each frame including at least one encoded parameter and a majority of the frames including a plurality of encoded parameters, the method comprising the steps of: (a) generating a frame timing signal indicative of the start of a new frame of data; (b) generating a parameter timing signal indicative of the start of a new encoded parameter; (c) loading a new encoded parameter from said memory means into an input register associated with said speech synthesis circuit in timed relation with said parameter timing signal unless inhibited by an inhibit signal; (d) testing the first encoded parameter loaded into said input register after the occurrence of said frame timing signal to determine whether said first encoded parameter is a preselected code; and (e) generating said inhibit signal until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal if said first encoded parameter is in the preselected code.
Claim 2
Independent Claim
189 words
A method of decoding encoded variable frame length data being coupled to a speech synthesis circuit from a memory means storing said encoded variable frame length data, each frame including at least one encoded parameter and a majority of the frames including a plurality of encoded parameters, the method comprising the steps of: (a) generating a frame timing signal indicative of the start of a new frame of data; (b) generating a parameter timing signal indicative of the start of a new encoded parameter; (c) loading a new encoded parameter from said memory means into an input register associated with said speech synthesis circuit in timed relation with said parameter timing signal unless inhibited by an inhibit signal; (d) testing the first encoded parameter loaded into said input register after the occurrence of said frame timing signal to determine whether said first encoded parameter is a preselected code; and (e) generating said inhibit signal until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal if said first encoded parameter is in the preselected code.
Claim 3
Dependent Claim
122 words
The method according to claim 1, wherein the second encoded parameter in a frame is also indicative of the length of said frame and further including the steps of: (a) testing the second encoded parameter loaded into said input register after the occurrence of said frame timing signal to determine whether said second encoded parameter is a preselected code; and (b) when said second encoded parameter is a preselected code, generating said inhibit signal: (i) after at least three of said encoded parameters have been inputted to said speech synthesis circuit via said input register, and (ii) until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal.
Claim 4
Dependent Claim
107 words
The method according to either claim 1 or 2, wherein a repeat bit is included among said encoded parameters in each frame of data having a plurality of encoded parameters and further including the steps of: (a) testing the state of said repeat bit; and (b) when said repeat bit is of a preselected state, generating said inhibit signal: (i) after at least two of said encoded parameters have been inputted to said speech synthesis circuit via said input register; and (ii) until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal.
Claim 5
Independent Claim
214 words
A method of decoding encoded variable frame length data being coupled to a speech synthesis circuit from a memory means storing said encoded variable frame length data, each frame including at least one encoded parameter and a majority of the frames including a plurality of encoded parameters, the second encoded parameter in a frame being indicative of the length of said frame, the method comprising the steps of: (a) generating a frame timing signal indicative of the start of a new frame of data; (b) generating a parameter timing signal indicative of the start of a new encoded parameter; (c) loading encoded parameters from said memory means into an input register associated with said speech synthesis circuit in timed relation with said parameter timing signal unless inhibited by an inhibit signal; (d) testing the second encoded parameter loaded into said input register after the occurrence of said frame timing signal to determine whether said second encoded parameter is a preselected code; and (e) generating said inhibit signal: (i) after a plurality of said encoded parameters have been inputted to said speech synthesis circuit via said input register; and (ii) until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal.
Claim 6
Independent Claim
214 words
A method of decoding encoded variable frame length data being coupled to a speech synthesis circuit from a memory means storing said encoded variable frame length data, each frame including at least one encoded parameter and a majority of the frames including a plurality of encoded parameters, the second encoded parameter in a frame being indicative of the length of said frame, the method comprising the steps of: (a) generating a frame timing signal indicative of the start of a new frame of data; (b) generating a parameter timing signal indicative of the start of a new encoded parameter; (c) loading encoded parameters from said memory means into an input register associated with said speech synthesis circuit in timed relation with said parameter timing signal unless inhibited by an inhibit signal; (d) testing the second encoded parameter loaded into said input register after the occurrence of said frame timing signal to determine whether said second encoded parameter is a preselected code; and (e) generating said inhibit signal: (i) after a plurality of said encoded parameters have been inputted to said speech synthesis circuit via said input register; and (ii) until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal.
Claim 7
Dependent Claim
104 words
The method according to claim 4, wherein a repeat bit is included among said encoded parameters in each frame of data having a plurality of encoded parameters and further including the steps of: (a) testing the state of said repeat bit; and (b) when said repeat bit is of a preselected state, generating said inhibit signal: (i) after at least two of said encoded parameters have been inputted to said speech synthesis circuit via said input register; and (ii) until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal.
Claim 8
Dependent Claim
84 words
The method according to either claim 4 or 5, further including the steps of: (a) testing the first encoded parameter loaded into said input register after the occurrence of said frame timing signal to determine whether the first encoded parameter is a preselected code; and (b) generating said inhibit signal until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal when said first encoded parameter is the preselected code.
Claim 9
Independent Claim
192 words
A method of decoding encoded variable frame length data being coupled to a speech synthesis circuit from a memory means storing said encoded variable frame length data, each frame including at least one encoded parameter and a majority of frames including a plurality of encoded parameters and a repeat bit, the method comprising the steps of: (a) generating a frame timing signal indicative of the start of a new frame of data; (b) generating a parameter timing signal indicative of the start of a new encoded parameter; (c) loading a new encoded parameter from said memory means into an input register associated with said speech synthesis circuit in timed relation with said parameter timing signal unless inhibited by an inhibit signal; (d) testing the state of said repeat bit; and (e) when said repeat bit is of a preselected state, generating said inhibit signal: (i) after at least two of said encoded parameters have been inputted to said speech synthesis circuit via said input register; and (ii) until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal.
Claim 10
Independent Claim
192 words
A method of decoding encoded variable frame length data being coupled to a speech synthesis circuit from a memory means storing said encoded variable frame length data, each frame including at least one encoded parameter and a majority of frames including a plurality of encoded parameters and a repeat bit, the method comprising the steps of: (a) generating a frame timing signal indicative of the start of a new frame of data; (b) generating a parameter timing signal indicative of the start of a new encoded parameter; (c) loading a new encoded parameter from said memory means into an input register associated with said speech synthesis circuit in timed relation with said parameter timing signal unless inhibited by an inhibit signal; (d) testing the state of said repeat bit; and (e) when said repeat bit is of a preselected state, generating said inhibit signal: (i) after at least two of said encoded parameters have been inputted to said speech synthesis circuit via said input register; and (ii) until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal.
Claim 11
Dependent Claim
81 words
The method according to claim 7, further including the steps of: (a) testing the first encoded parameter loaded into said input register after the occurrence of said frame timing signal to determine whether the first encoded parameter is a preselected code; and (b) generating said inhibit signal until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal when said first encoded parameter is the preselected code.
Claim 12
Dependent Claim
100 words
The method according to claim 7 or 8, further including the steps of: (a) testing the second encoded parameter loaded into said input register after the occurrence of said frame timing signal to determine whether the speech is voiced or unvoiced; and (b) when said speech is unvoiced, generating said inhibit signal: (i) after at least three of said encoded parameters have been inputted to said speech synthesis circuit via said input register; and (ii) until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal.
Claim 13
Dependent Claim
343 words
A speech synthesis system comprising: (a) memory means for storing variable frame length data, said variable frame length data including encoded variable length speech parameters representative of pitch, energy and filter coefficients, each frame of said variable frame length data including at least one encoded parameter; (a) control means coupled to said memory means for selectively addressing said variable frame length data; (c) speech synthesis means coupled to said memory means for converting said encoded variable length speech parameters into analog signals representative of human speech, said speech synthesis means including: a parametric data converter comprising: (i) timing means for generating a frame timing signal indicative of the start of a frame of data as well as parameter timing signals indicative of the start of each encoded parameter in a frame: (ii) an input register, coupled to said memory means, whose length is sufficient to accommodate the longest of said encoded parameters; (iii) an input register control means coupled to said input register and said timing means for controlling the inputting of said encoded speech parameters into said input register in timed relationship with said parameter timing signals generated by said timing means, in the absence of an inhibit signal, and for prohibiting the inputting of said encoded speech parameters into said input register in the presence of an inhibit signal; (iv) first circuit means, coupled to said input register and said timing means, for testing a first encoded parameter in a frame of data to determine whether said frame contains only one encoded parameter, said first encoded parameter having at least one preselected code indicating said frame of data contains only one encoded parameter; and (v) second circuit means, coupled to said first circuit means and said timing means for generating said inhibit signal in response to said first circuit means detecting said at least one preselected code, said inhibit signal being generated until said timing means indicates the start of a next frame of data; and (d) audio means for converting said analog signals representative of human speech into audible sounds.
Claim 14
Dependent Claim
343 words
A speech synthesis system comprising: (a) memory means for storing variable frame length data, said variable frame length data including encoded variable length speech parameters representative of pitch, energy and filter coefficients, each frame of said variable frame length data including at least one encoded parameter; (a) control means coupled to said memory means for selectively addressing said variable frame length data; (c) speech synthesis means coupled to said memory means for converting said encoded variable length speech parameters into analog signals representative of human speech, said speech synthesis means including: a parametric data converter comprising: (i) timing means for generating a frame timing signal indicative of the start of a frame of data as well as parameter timing signals indicative of the start of each encoded parameter in a frame: (ii) an input register, coupled to said memory means, whose length is sufficient to accommodate the longest of said encoded parameters; (iii) an input register control means coupled to said input register and said timing means for controlling the inputting of said encoded speech parameters into said input register in timed relationship with said parameter timing signals generated by said timing means, in the absence of an inhibit signal, and for prohibiting the inputting of said encoded speech parameters into said input register in the presence of an inhibit signal; (iv) first circuit means, coupled to said input register and said timing means, for testing a first encoded parameter in a frame of data to determine whether said frame contains only one encoded parameter, said first encoded parameter having at least one preselected code indicating said frame of data contains only one encoded parameter; and (v) second circuit means, coupled to said first circuit means and said timing means for generating said inhibit signal in response to said first circuit means detecting said at least one preselected code, said inhibit signal being generated until said timing means indicates the start of a next frame of data; and (d) audio means for converting said analog signals representative of human speech into audible sounds.
Claim 15
Dependent Claim
57 words
The speech synthesis system according to claim 10 wherein said parametric data converter further includes means for testing a second encoded parameter in a frame of data to determine whether said frame contains only two encoded parameters, said second encoded parameter having at least one preselected code indicating said frame of data contains only two encoded parameters.
Claim 16
Dependent Claim
55 words
The system according to claim 11 wherein said parametric data converter further includes means for testing a second encoded parameter in a frame of data to determine whether said frame contains only three encoded parameters, said second encoded parameter having at least one preselected code indicating said frame of data contains only three encoded parameters.
Claim 17
Dependent Claim
32 words
The system according to claim 10 wherein said parametric data converter further includes an encoded parameter storage means, coupled to said input register, for storing encoded parameters inputted to said input register.
Claim 18
Dependent Claim
43 words
The system according to claim 13 wherein said parametric data converter further includes a digital storage means for storing a plurality of decoded parameters and means for addressing said digital storage means utilizing said encoded parameters stored in said encoded parameter storage means.
Claim 19
Dependent Claim
16 words
The system according to claim 14 wherein said digital storage means comprises a read only memory.
Claim 20
Dependent Claim
35 words
The system according to claim 10 wherein said first encoded parameter is indicative of an energy parameter and wherein the state of said energy parameter equal to zero is indicative of a pause during speech.
Claim 21
Dependent Claim
36 words
The system according to claim 12, wherein said second encoded parameter is indicative of a repeat frame in which said three encoded parameters are indicative of an energy parameter, a repeat parameter and a pitch parameter.
Claim 22
Dependent Claim
70 words
The system according to claim 12 wherein said parametric data converter further includes means for testing a third encoded parameter in a frame of data to determine whether said frame of data contains some preselected number of parameters, said preselected number being less than the maximum number of parameters, said third encoded parameter having at least one preselected code indicating said frame of data contains said preselected number of parameters.
Claim 23
Dependent Claim
35 words
The system according to claim 18 wherein said third encoded parameter is indicative of a pitch parameter and wherein the state of said pitch parameter equal to zero is indicative of an unvoiced speech period.
Claim 24
Dependent Claim
17 words
The system according to claim 18 wherein said preselected number is six less than said maximum number.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-12-07 | 1985-06-08 | 1985-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-12-07 | 1989-06-08 | 1989-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-12-07 | 1993-06-08 | 1993-12-08 | $7700.00 | Window Closed / Lapsed |