US4303838A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Master-slave flip-flop circuits
Assignee: ZF International UK Ltd
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Filing: 1979-05-14
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Granted: 1981-12-01
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Expires: 1999-05-14
Abstract
Abstract A d.c. triggered master-slave flip-flop circuit including a master flip-flop with a capacitive delay means at its input, and a slave flip-flop having its input connected to the output of the master flip-flop. A capacitive delay means is connected at the input of the slave flip-flop. The slave flip-flop controls the connections at the input of the master flip-flop in known manner. The two capacitive delay means, serve to make each flip-flop circuit immune to noise pulses and also eliminate multiple triggering caused by contact bounce when the circuit is controlled by mechanical contacts.
Inventors
- 👤 Kenneth W. Lambert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:32
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/013; B; B60; B60S; B60S1/00; B60S1/02; B60S1/04; B60S1/06; B60S1/08; B60S1/0803; B60S1/0807; H03K3/02; H03K3/023
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
190 words
A d.c.-triggered master-slave flip-flop circuit for operation in conjunction with a signal source, said circuit comprising: a master flip-flop circuit having an input and an output, the voltage at said input determining the state of the master flip-flop circuit; means providing positive feedback from the output to the input of the master flip-flop circuit; slave circuit means, having an input and an output, for alternatively connecting said signal source and said output of said slave circuit means to said master flip-flop circuit input; means connecting said input of said slave circuit means to said output of said master flip-flop circuit; capacitive delay means, connected to the input of each of the master flip-flop circuit and the slave circuit means, for rendering the master flip-flop circuit and the slave circuit means immune to noise pulses and unintended multiple triggering; wherein each of the master flip-flop circuit and the slave circuit means includes a d.c. input and incorporates current source means controllable by the d.c. input to charge and discharge the associated capacitive delay means; and comparator means connected to compare the voltage on said capacitive delay means with a reference voltage.
Claim 2
Dependent Claim
190 words
A d.c.-triggered master-slave flip-flop circuit for operation in conjunction with a signal source, said circuit comprising: a master flip-flop circuit having an input and an output, the voltage at said input determining the state of the master flip-flop circuit; means providing positive feedback from the output to the input of the master flip-flop circuit; slave circuit means, having an input and an output, for alternatively connecting said signal source and said output of said slave circuit means to said master flip-flop circuit input; means connecting said input of said slave circuit means to said output of said master flip-flop circuit; capacitive delay means, connected to the input of each of the master flip-flop circuit and the slave circuit means, for rendering the master flip-flop circuit and the slave circuit means immune to noise pulses and unintended multiple triggering; wherein each of the master flip-flop circuit and the slave circuit means includes a d.c. input and incorporates current source means controllable by the d.c. input to charge and discharge the associated capacitive delay means; and comparator means connected to compare the voltage on said capacitive delay means with a reference voltage.
Claim 3
Dependent Claim
57 words
A flip-flop circuit as claimed in claim 1 in which said current source means comprises a constant current sink circuit providing a constant charging current for the associated capacitive delay means, and a switchable constant current source circuit controlled by the d.c. input and providing when operative a constant discharging current for said associated capacitive delay means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-11-30 | 1985-06-01 | 1985-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-11-30 | 1989-06-01 | 1989-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-11-30 | 1993-06-01 | 1993-12-01 | $7700.00 | Window Closed / Lapsed |