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US4302764A Expired / Lapsed US ⏱️ 0.0 years remaining

Nondestructive read-out dynamic memory cell

Assignee: International Business Machines Corp
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Filing: 1979-06-29
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Granted: 1981-11-24
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Expires: 1999-06-29
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Abstract

Abstract A MOSFET which is capable of being placed in two states, one of which is quasi-stable and a memory cell which includes such a device is disclosed. The device basically consists of a pair of diffusions of one conductivity type disposed in a substrate of opposite conductivity type. The channel region between the diffusions is ion implanted or diffused with a dopant which forms a channel of the same conductivity type as the diffusions. A gate electrode is spaced from the channel region by a thin oxide and the gate and substrate are biased so that two states of the device are possible. One is a stable, equilibrium or conducting state wherein an opposite conductivity type inversion layer is formed at the surface of the now buried channel. Another state is a quasi-stable, nonequilibrium, nonconductive state wherein the channel region between the diffusions is depleted of mobile charge carriers. This latter state, after a relatively long period of time in the order of several minutes to hours, decays to the stable or conducting state. By applying appropriately poled pulses to the gate or source of the device, the device may be switched from one of the two conducting states to the other. A dynamic memory cell which includes an addressing FET utilizes the device described above. A word line is connected to the gate of an addressing FET which utilizes as its drain the source of the storage device described above while a bit line is connected to the source of the addressing FET. The latter, when rendered conductive by a potential on its gate, applies appropriate write pulses from a pulsed source to place the storage device in one of its two possible states. One embodiment utilizes an annular or enclosed channel device while a memory cell embodiment utilizes an open channel device, the surface of the channel of which is isolated from the substrate by a surrounding recessed oxide (ROX). The channel surface isolation of the storage device is a requirement without which leakage from substrate to the surface would not permit the achievement of the two states of the device. The quasi-stable state remains for a time which is sufficient for most memory purposes and, to the extent that longer times are required, refreshing of the states is available.

Inventors

  • 👤 Frank F. Fang
  • 👤 Hwa N. Yu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 12:21
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/35; G11C16/00; G11C16/02; G11C16/04; G11C16/0466

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 171 words
An array of semiconductor storage devices each semiconductor storage device comprising, a semiconductor substrate of one conductivity type, a source and drain region of opposite conductivity type disposed in said substrate and a channel region of said opposite conductivity type disposed between and interconnecting said source and drain regions the surface of said channel region being in electrically isolated relationship with the surface of said substrate outside of said channel region, a gate electrode disposed in insulated spaced relationship with said channel region, means connected to said device for applying a first voltage of one polarity for forming an inversion layer at the surface of said channel region rendering said device conductive and for applying a second voltage of opposite polarity for forming a depletion region between said source and drain regions rendering said device non-conductive, and, means connected to said gate electrode and said substrate for applying a fixed value of bias voltage to maintain said inversion layer or said depletion region after said first or second voltage is applied.
Claim 2
Dependent Claim 171 words
An array of semiconductor storage devices each semiconductor storage device comprising, a semiconductor substrate of one conductivity type, a source and drain region of opposite conductivity type disposed in said substrate and a channel region of said opposite conductivity type disposed between and interconnecting said source and drain regions the surface of said channel region being in electrically isolated relationship with the surface of said substrate outside of said channel region, a gate electrode disposed in insulated spaced relationship with said channel region, means connected to said device for applying a first voltage of one polarity for forming an inversion layer at the surface of said channel region rendering said device conductive and for applying a second voltage of opposite polarity for forming a depletion region between said source and drain regions rendering said device non-conductive, and, means connected to said gate electrode and said substrate for applying a fixed value of bias voltage to maintain said inversion layer or said depletion region after said first or second voltage is applied.
Claim 3
Dependent Claim 22 words
A semiconductive storage device according to claim 1 further including means connected to said device for reading the state of said device.
Claim 4
Dependent Claim 51 words
A semiconductive storage device according to claim 1 wherein said means for applying first and second voltages to said device includes means connected to said gate electrode for applying a pulse of one polarity to render said device conductive and a pulse of the opposite polarity to render said device non-conductive.
Claim 5
Dependent Claim 51 words
A semiconductive storage device according to claim 1 wherein said means for applying first and second voltages to said device includes means connected to said source region for applying a pulse of one polarity to render said device conductive and a pulse of the opposite polarity to render said device non-conductive.
Claim 6
Dependent Claim 46 words
A semiconductive storage device according to claim 1 wherein one of said source and drain regions surrounds the other of said regions forming an annular channel region and wherein said gate electrode is annular, said regions and said gate electrode forming an annular field effect transistor.
Claim 7
Dependent Claim 26 words
A semiconductor device according to claim 1 further including means disposed at the extremites of said channel region for isolating the surface thereof from said substrate.
Claim 8
Dependent Claim 25 words
A semiconductor device according to claim 6 wherein said means for isolating includes a recessed oxide region disposed at the extremities of said channel region.
Claim 9
Dependent Claim 233 words
An array of memory cells each memory cell comprising, a semiconductor substrate of one conductivity type, first, second and third regions of opposite conductivity type disposed in said substrate said first and second regions having a channel region of said opposite conductivity type disposed between and interconnecting said first and second regions and forming a storage device the surface of said channel region of opposite conductivity type being in electrically isolated relationship with the surface of said substrate outside of said channel regions said second and third regions having a channel region of said one conductivity type disposed between said second and third regions and forming an addressing device, a gate electrode disposed in insulated space relationship with each of said channel regions, means connected to said addressing device for applying a first voltage of one polarity for forming an inversion layer at the surface of said channel region of said storage device rendering said storage device conductive and for applying a second voltage of opposite polarity for forming a depletion region between said first and second regions rendering said storage device non-conductive, means connected to said gate electrode and said substrate of said storage device for applying a fixed value of bias voltage to maintain said inversion layer or said depletion region after said first or second voltage is applied, and, means connected to said addressing device for selecting said storage device.
Claim 10
Dependent Claim 233 words
An array of memory cells each memory cell comprising, a semiconductor substrate of one conductivity type, first, second and third regions of opposite conductivity type disposed in said substrate said first and second regions having a channel region of said opposite conductivity type disposed between and interconnecting said first and second regions and forming a storage device the surface of said channel region of opposite conductivity type being in electrically isolated relationship with the surface of said substrate outside of said channel regions said second and third regions having a channel region of said one conductivity type disposed between said second and third regions and forming an addressing device, a gate electrode disposed in insulated space relationship with each of said channel regions, means connected to said addressing device for applying a first voltage of one polarity for forming an inversion layer at the surface of said channel region of said storage device rendering said storage device conductive and for applying a second voltage of opposite polarity for forming a depletion region between said first and second regions rendering said storage device non-conductive, means connected to said gate electrode and said substrate of said storage device for applying a fixed value of bias voltage to maintain said inversion layer or said depletion region after said first or second voltage is applied, and, means connected to said addressing device for selecting said storage device.
Claim 11
Dependent Claim 24 words
A memory cell according to claim 8 further including means connected to said storage device and said addressing device for reading said memory cell.
Claim 12
Dependent Claim 45 words
A memory cell according to claim 8 wherein said means for applying includes means connected to said first region for applying a pulse of one polarity to render said storage device conductive and a pulse of the opposite polarity to render said storage device non-conductive.
Claim 13
Dependent Claim 39 words
A memory cell according to claim 8 wherein means for selecting includes a word line connected to said gate electrode of said addressing device and a pulsed source connected to said word line for rendering said addressing device conductive.
Claim 14
Dependent Claim 33 words
A memory cell according to claim 8 further including means disposed at the extremities of said channel regions for isolating the surface of said channel region of said storage device from said substrate.
Claim 15
Dependent Claim 29 words
A memory cell according to claim 12 wherein said means for isolating includes a recessed oxide region disposed at the extremities of said channel region of said storage device.

References Cited (Backward Citations)

US3952325A Cited
US4053915A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-11-23 1985-05-25 1985-11-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-11-23 1989-05-25 1989-11-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-11-23 1993-05-25 1993-11-24 $7700.00 Window Closed / Lapsed

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