Delay line compensation network

Claim 2

A timing generator circuit for generating a sequence of output timing pulses in response to input timing pulses, said circuit comprising: a first multisection delay line having an input terminal for receiving said input timing pulses, a plurality of taps and an output tap; a second multisection delay line having an input terminal directly coupled to said output tap of said first delay line and a plurality of taps and an output tap; and, capacitive means having first and second terminals for connecting said capacitive means between predetermined taps connected to last and first sections of said first and second multisection delay lines forming a compensating network with the corresponding sections of said delay lines for cancelling voltage reflections produced by connecting said first and second delay lines in series.

Claim 3

The generator circuit of claim 1 wherein said capacitive means is a capacitor.

Claim 4

The generator circuit of claim 1 wherein each of said first and second delay lines are constructed to provide the same predetermined increment of delay between successive ones of said plurality of taps and wherein said predetermined taps of said first and second delay lines correspond to a last one of said plurality of taps connected at the input of said last section and a first one of said plurality of said taps respectively connected at the output of said first section for enabling said capacitive means to apply voltage signals of the correct polarity and phase for cancelling said voltage reflections.

Claim 5

The generator circuit of claim 3 wherein each of said first and second delay lines have a plurality of inductor-capacitor sections constructed to provide the same predetermined electrical and delay characteristics for each of said plurality of sections for generating said sequence of output timing pulses with a minimum of distortion.

Claim 6

The generator circuit according to claim 4 wherein each of said inductor-capacitor sections has an input and an output, said last section of said first delay line has an input impedance Z1 which is greater in magnitude than an input impedance Z2 of said first section of said second delay line producing voltage reflections in response to the application of said input timing pulses to said input terminal of said second delay line.

Claim 7

The timing generator of claim 5 wherein said capacitive means is selected to have a value of capacitance wherein a first time constant of said compensating network formed by said capacitive means and impedance Z2 is less in magnitude than a second time constant of said compensating network formed by said capacitive means and said impedance Z1 for cancelling said voltage reflections without adversely affecting the characteristics of said output timing pulses.

Claim 8

The timing generator of claim 6 wherein said value of capacitance is 68 picofarads.

Claim 9

A timing generator circuit for generating a sequence of output timing pulses in response to input timing pulses, said circuit comprising: a first delay line having a plurality of like constructed sections, an input terminal for receiving said input timing pulses, a plurality of taps and an output tap; a second delay line having a plurality of said like constructed sections, an input terminal directly coupled to said first delay line output tap, a plurality of taps and an output tap; capacitive means having first and second terminals for connecting said capacitive means between predetermined taps connected to last and first sections of said first and second delay lines forming a compensating network with said last and first sections of said delay lines, said network being operative in response to said input timing pulses to apply voltage signals of sufficient amplitude, correct phase and polarity to cancel with voltage spikes generated by connecting said first and second delay lines in series.

Claim 10

A timing generator circuit for generating a sequence of output timing pulses in response to input timing pulses, said circuit comprising: a first delay line having a plurality of like constructed sections, an input terminal for receiving said input timing pulses, a plurality of taps and an output tap; a second delay line having a plurality of said like constructed sections, an input terminal directly coupled to said first delay line output tap, a plurality of taps and an output tap; capacitive means having first and second terminals for connecting said capacitive means between predetermined taps connected to last and first sections of said first and second delay lines forming a compensating network with said last and first sections of said delay lines, said network being operative in response to said input timing pulses to apply voltage signals of sufficient amplitude, correct phase and polarity to cancel with voltage spikes generated by connecting said first and second delay lines in series.

Claim 11

The generator circuit of claim 8 wherein said capacitive means is a capacitor.

Claim 12

The generator circuit of claim 8 wherein each of said first and second delay lines are constructed to provide the same predetermined increment of delay between successive ones of said plurality of taps and wherein said predetermined taps of said first and second delay lines correspond to a last one of said plurality of taps connected at the input of said last section and a first one of said plurality of said taps connected at the output of said first section.

Claim 13

The generator circuit of claim 10 wherein each of said first and second delay lines have a plurality of inductor-capacitor sections constructed to provide the same predetermined electrical and delay characteristics for each of said plurality of sections for generating said sequence of output timing pulses with a minimum of distortion.

Claim 14

The generator circuit according to claim 11 wherein each of said inductor-capacitor sections has an input and an output, said last section of said first delay line has an input impedance Z1 which is greater in magnitude than an input impedance Z2 of said first section of said second delay line producing negative voltage reflections in response to the application of said input timing pulses to said input terminal of said second delay line.

Claim 15

The timing generator of claim 12 wherein said capacitive means is selected to have a value of capacitance wherein a first time constant of said compensating network formed by said capacitive means and impedance Z2 is less in magnitude than a second time constant of said compensating network formed by said capacitive means and said impedance Z1 for cancelling said voltage reflections without adversely affecting the characteristics of said output timing pulses.

Claim 16

The timing generator of claim 13 wherein said value of capacitance is 68 picofarads.

Claim 17

A timing generator circuit for generating a sequence of output timing pulses in response to input timing pulses, said circuit comprising: first and second delay lines having a number of sections, and input terminal and a corresponding number of taps and an output tap, said first delay line input terminal being connected to receive said input timing pulses and said first delay line output tap being directly connected to said second delay line input terminal; and, a compensating network comprising: a last one of said number of sections of said first delay line; a first one of said number of sections of said second delay line; and, capacitive means having first and second terminals, said first terminal and second terminals being connected between said first one of said sections of said second delay line and said last one of said sections of said first delay line respectively, said compensating network being operative in response to said input timing pulses to apply voltage signals of predetermined polarities and phase for cancelling voltage reflections produced by connecting said first and second delay lines in series.

Claim 18

A timing generator circuit for generating a sequence of output timing pulses in response to input timing pulses, said circuit comprising: first and second delay lines having a number of sections, and input terminal and a corresponding number of taps and an output tap, said first delay line input terminal being connected to receive said input timing pulses and said first delay line output tap being directly connected to said second delay line input terminal; and, a compensating network comprising: a last one of said number of sections of said first delay line; a first one of said number of sections of said second delay line; and, capacitive means having first and second terminals, said first terminal and second terminals being connected between said first one of said sections of said second delay line and said last one of said sections of said first delay line respectively, said compensating network being operative in response to said input timing pulses to apply voltage signals of predetermined polarities and phase for cancelling voltage reflections produced by connecting said first and second delay lines in series.

Claim 19

The generator circuit of claim 15 wherein said capacitive means is a capacitor.

Claim 20

The generator circuit of claim 16 wherein each of said number of sections of said first and second delay lines are constructed from inductor-capacitor elements to provide the same predetermined electrical and delay characteristics for generating said sequence of output timing pulses with a minimum of distortion.

Claim 21

The generator circuit according to claim 17 wherein each of said inductor-capacitor sections has an input and an output, said last one of said sections of said first delay line has an input impedance Z1 which is greater in magnitude than an input impedance Z2 of said first one of said sections of said second delay line producing negative voltage reflections in response to the application of said input timing pulses to said input terminal of said second delay line.

Claim 22

The timing generator of claim 18 wherein said capacitive means is selected to have a value of capacitance wherein a first time constant of said compensating network corresponding to said capacitive means and impedance Z2 is less in magnitude than a second time constant of said compensating network corresponding to said capacitive means and said impedance Z1 for cancelling said voltage reflections without adversely affecting the characteristics of said output timing pulses.

Claim 23

The timing generator of claim 19 wherein said value of capacitance is 68 picofarads.