US4298961A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bipolar memory circuit
Assignee: Hitachi Ltd
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Filing: 1980-04-16
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Granted: 1981-11-03
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Expires: 2000-04-16
Abstract
Abstract An emitter junction type bipolar memory cell circuit having clamp diodes connected in parallel to collector resistances. The collector resistances are set to produce a potential difference of greater than 0.6 V or so caused by the stationary current. By so doing, it is possible to exclude any mal-function attributable to noises in the writing operation of the memory circuit.
Inventors
- 👤 Atsuo Hotta
- 👤 Yukio Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:32
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; G11C11/413; G11C11/414; G11C11/416
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
177 words
A memory circuit comprising: a matrix of memory cells arranged in rows and columns, each cell having a pair of multi-emitter transistors each of which having two emitters, collector and a base, the bases and collectors of said pair of multi-emitter transistors being cross-coupled to each other, one emitters of said pair of transistors being commonly connected to a stationary current source for providing a stationary current, whereas the other emitters of said pair of transistors being respectively connected to a pair of column lines, said collectors of said pair of transistors being connected to a row line through parallel circuits of a load resistance and a diode means, respectively; a pair of writing transistors being connected at their emitters to said pair of column lines respectively; and writing current source means connected to said pair of column lines for delivering a writing current; wherein, in the stationary state out of selection, the difference of collector voltages between said pair of multi-emitter transistors caused by the stationary current is set at a level higher than 0.6 V.
Claim 2
Dependent Claim
177 words
A memory circuit comprising: a matrix of memory cells arranged in rows and columns, each cell having a pair of multi-emitter transistors each of which having two emitters, collector and a base, the bases and collectors of said pair of multi-emitter transistors being cross-coupled to each other, one emitters of said pair of transistors being commonly connected to a stationary current source for providing a stationary current, whereas the other emitters of said pair of transistors being respectively connected to a pair of column lines, said collectors of said pair of transistors being connected to a row line through parallel circuits of a load resistance and a diode means, respectively; a pair of writing transistors being connected at their emitters to said pair of column lines respectively; and writing current source means connected to said pair of column lines for delivering a writing current; wherein, in the stationary state out of selection, the difference of collector voltages between said pair of multi-emitter transistors caused by the stationary current is set at a level higher than 0.6 V.
Claim 3
Dependent Claim
62 words
A memory circuit as claimed in claim 1, wherein, in the stationary state, the potential drop generated by said stationary current across said load resistance of the conductive multi-emitter transistor in said memory cell is produced by applying a bias of higher than 0.6 V to the diode connected in parallel to said load resistance in the forward direction of said diode.
Claim 4
Dependent Claim
19 words
A memory circuit as claimed in claim 2, wherein said memory cell include capacitors connected to respective load resistances.
References Cited (Backward Citations)
US3781828A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-11-02 | 1985-05-04 | 1985-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-11-02 | 1989-05-04 | 1989-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-11-02 | 1993-05-04 | 1993-11-03 | $7700.00 | Window Closed / Lapsed |