US4298879A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect transistor
Assignee: Fujitsu Ltd
•
Filing: 1980-02-04
•
Granted: 1981-11-03
•
Expires: 2000-02-04
Abstract
Abstract In a field effect transistor having interdigital electrodes the gate bonding pad portion is situated in the space formed between a pair of adjacent divided portions of the active region of the field effect transistor.
Inventors
- 👤 Yutaka Hirano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:30
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/30; H10D; H10D30/00; H10D30/80; H10D30/87; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519; H10W99/00; H10W72/351; H10W72/352; H10W72/50; H10W72/531; H10W72/5363; H10W72/851; H10W72/874; H10W72/884
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
95 words
A transistor device having interdigital electrodes on a surface of a semiconductor body, said device comprising an insulating substrate, a plurality of active semiconductor regions placed on said insulating substrate, source and drain electrodes placed on said plurality of active semiconductor regions, said source and drain electrodes being interconnected at the opposite ends with contact pad areas, respectively, and gate electrodes placed between said source and drain electrodes and connected together with a gate contact pad area, said gate contact pad area being placed between a pair of adjacent ones of said active semiconductor regions.
Claim 2
Dependent Claim
95 words
A transistor device having interdigital electrodes on a surface of a semiconductor body, said device comprising an insulating substrate, a plurality of active semiconductor regions placed on said insulating substrate, source and drain electrodes placed on said plurality of active semiconductor regions, said source and drain electrodes being interconnected at the opposite ends with contact pad areas, respectively, and gate electrodes placed between said source and drain electrodes and connected together with a gate contact pad area, said gate contact pad area being placed between a pair of adjacent ones of said active semiconductor regions.
Claim 3
Dependent Claim
23 words
The device of claim 1, comprising a portion of said source electrode intervening between said drain electrode and said gate contact pad area.
Claim 4
Dependent Claim
21 words
The device of claim 1, said source electrode providing said device with source electrode inductance of as low as 20 pH.
Claim 5
Dependent Claim
18 words
The device of claim 3 with a maximum available gain of at least 3 dB at 8 GHz.
Claim 6
Dependent Claim
27 words
The device of claim 3 or 4, said device being operable in the range from 3 to 18 GHz as a result of said low inductance electrode.
References Cited (Backward Citations)
US3969745A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-11-02 | 1985-05-04 | 1985-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-11-02 | 1989-05-04 | 1989-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-11-02 | 1993-05-04 | 1993-11-03 | $7700.00 | Window Closed / Lapsed |