Symbol generator for a graphic console

Claim 2

A symbol generator for tracing, on a sensitive medium, alphanumeric characters and the like, said characters being formed on a grid comprising l.P adjacent columns, each column comprising m.Q points, said generator comprising: (a) first and second input busses, each connectable to an external control means (MPU), said first bus comprising a data channel (MPDB) and said second bus comprising an address channel (MPAB); (b) means for supplying a clock signal (CKIN) to control the timing of said symbol generator; (c) a character memory (65), connected to said first and second input busses, said memory having lX m memory calls for each character and further comprising:

Claim 3

first and second addressing inputs; and 2. a signal output for driving said sensitive medium; (d) a writing pointer circuit (66) connected to said first and second input busses, said pointer circuit comprising first (X) and second (Y) up/down counters connected to said clock signal supplying means, each of said counters having first (ENX) and second (ENY) enabling inputs and a command input (U/DY) for setting the counter to count up or count down, the outputs of said up/down counters respectively comprising the X and Y address inputs for the means driving said sensitive medium; and (e) a writing circuit (61), connected to said first and second input busses and to said clock signal supplying means, said writing circuit including means, responsive to the factors P and Q, for programming said writing circuit, said writing circuit having first, second, and third outputs respectively corresponding and connected to the first and second enabling inputs and the command input of said writing pointer circuit, and first and second address outputs respectively corresponding and connected to the first and second addressing inputs of said character memory.

Claim 4

first and second addressing inputs; and 2. a signal output for driving said sensitive medium; (d) a writing pointer circuit (66) connected to said first and second input busses, said pointer circuit comprising first (X) and second (Y) up/down counters connected to said clock signal supplying means, each of said counters having first (ENX) and second (ENY) enabling inputs and a command input (U/DY) for setting the counter to count up or count down, the outputs of said up/down counters respectively comprising the X and Y address inputs for the means driving said sensitive medium; and (e) a writing circuit (61), connected to said first and second input busses and to said clock signal supplying means, said writing circuit including means, responsive to the factors P and Q, for programming said writing circuit, said writing circuit having first, second, and third outputs respectively corresponding and connected to the first and second enabling inputs and the command input of said writing pointer circuit, and first and second address outputs respectively corresponding and connected to the first and second addressing inputs of said character memory.

Claim 5

The generator according to claim 1 wherein said character is formed on the grid by traversing the l.P columns, of m.Q points each, according to a pedestal trajectory, said generator further comprising: (f) means for generating the l.P adjacent columns comprising the columns of said grid, said means including: 1. a uni-directional, synchronous counter (62) comprising a modulo-l counter (62b) chained to a modulo-P counter (62a);

Claim 6

a recognition circuit (62D,F) connected to the outputs of said modulo-l and modulo-P counters for recognizing the state of the outputs thereof; and 3. a parity counter (62C) for generating a count representative of the parity of the columns in said grid.

Claim 7

a recognition circuit (62D,F) connected to the outputs of said modulo-l and modulo-P counters for recognizing the state of the outputs thereof; and 3. a parity counter (62C) for generating a count representative of the parity of the columns in said grid.

Claim 8

The generator according to claim 2 further comprising: (g) a register (62E) for storing the value of the factor P, said modulo-P counter including a plurality of inputs each connected to a corresponding output of said P-factor storing register.

Claim 9

The generator according to claim 3 wherein said recognition circuit comprises: (h) at least a recognition logic circuit (62D), connected to the outputs of said modulo-P counter, for recognizing the state-2 in said counter.

Claim 10

The generator according to claim 4 wherein said recognition circuit further comprises: (i) a recognition stage (62F), connected to the outputs of said modulo-l counter, for recognizing the state l'<l said modulo-l counter, said recognition stage further comprising an enabling input (QUAD).

Claim 11

The generator according to claim 1 wherein said character is formed on the grid by traversing the l.P columns, of m.Q points each, according to a pedestal trajectory, said generator further comprising: (j) means for generating the m.Q points in each column of the grid, including: 1. a bi-directional, synchronous counter (63) comprising a modulo-Q counter (63a) chained to a modulo-m counter (63b); and

Claim 12

a recognition circuit (63E,H) connected to the outputs of said modulo-m and modulo-Q counters for recognizing the state of the outputs thereof.

Claim 13

a recognition circuit (63E,H) connected to the outputs of said modulo-m and modulo-Q counters for recognizing the state of the outputs thereof.

Claim 14

The generator according to claim 6, further comprising: (k) a register (63D) for storing the value of the factor Q, said modulo-Q counter including a plurality of inputs each connected to a corresponding output of said Q-factor storing register; and (l) means, intermediate said Q-storing register and said modulo-Q counter, for forcing the count in said modulo-Q counter to a particular count.

Claim 15

The generator according to claim 6 wherein said recognition circuit comprises: (m) at least a first and a second recognition stage, connected to the outputs of said modulo-Q counter, for respectively recognizing the states l and Q of said modulo-Q counter.

Claim 16

The generator according to claim 8 wherein said recognition circuit further comprises: (n) a third recognition stage (63H), connected to the outputs of said modulo-m counter, for recognizing the state m'<m in said modulo-m counter, said third recognition stage further including an enabling input (QUAD).

Claim 17

The generator according to claim 2 wherein said parity counter comprises a trigger circuit of the "T" type.

Claim 18

The generator according to claim 2 wherein said uni-directional synchronous counter further comprises: (o) a reset input for setting said "T" type trigger circuit and said modulo-l counter to the "zero" state and said modulo-P counter to the value "P."

Claim 19

The generator according to claim 5 wherein the output of said modulo-l recognition stage presets said modulo-l counter to the value l+2.

Claim 20

The generator according to claim 2 or claim 6, further comprising: (p) means for generating a first signal for enabling said modulo-P counter, a second signal for enabling said modulo-Q counter, a third signal for enabling said modulo-m counter and a fourth signal for enabling said parity trigger.

Claim 21

The generator according to claim 1, further comprising: (q) means for interrupting the operation of said writing circuit.

Claim 22

The generator according to claim 1 further comprising: (r) means for forcing the signal output of said character memory to a logical "high."

Claim 23

The generator according to claim 1 further comprising: (s) means for forcing the signal output of said character memory to a logical "low."

Claim 24

The generator according to claim 1 wherein said character memory comprises a read-only memory (ROM).

Claim 25

The generator according to claim 1 wherein said character memory comprises a programmable read-only memory (PROM).