US4296439A
Expired / Lapsed
US
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Digital signal control system in a facsimile communication
Assignee: KDDI Corp
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Filing: 1980-05-15
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Granted: 1981-10-20
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Expires: 2000-05-15
Abstract
Abstract In a digitalized facsimile transmission system, (k) number of scanning lines (k=2 or 4) are encoded to a relative address code and the next scanning line is encoded to a run length code, and each scanning line has the related synchronization code pattern corresponding either said relative address code or said run length code. Thus, the effect of a transmission error is restricted within one scanning line when that error occurs in the scanning line encoded to run length code, or k lines when that error occurs in the scanning line encoded to relative address code. The value (k) is switched between k=2 and k=4 according to the instantaneous quality of a communication line. When the quality is good, k=4 is selected, and when the quality is bad, k=2 is selected. The reception side can switch the decoding systems between relative address decode and run length decode, by being controlled through the related synchronization code patterns. A synchronization code pattern has a plurality of O's inserted between a pair of 1's (1000 . . . 0001), and the number of O's between said 1's indicates one of relative address code and run length code. In order to discriminate a facsimile information from a synchronization code pattern, when the facsimile information has the more continuous O's than (n), an idle signal having the value "1" is inserted in every (n-1) number of continuous O's of the facsimile information. Said idle signal is deleted automatically in the receiver.
Inventors
- 👤 Hiroichi Teramura
- 👤 Yasuhiro Yamazaki
- 👤 Yasushi Wakahara
- 👤 Naohiko Hattori
- 👤 Seiichi Yamamoto
- 👤 Kouzo Nakao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:22
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/32; H04N1/333; H04N1/33361; H04L; H04L7/00; H04L7/0079; H04L7/0083; H04N1/3333; H04N1/41; H04N1/411; H04N1/413; H04N2201/00; H04N2201/32; H04N2201/333; H04N2201/33307; H04N2201/33342; H04N2201/33357
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
198 words
A method for controlling a facsimile system characterized in that the scanning lines of a picture signal are encoded so that (k) number of continuous scanning lines are encoded by a relative address encoding system and the next one scanning line is encoded by run length encoding system and that sequence is repeated, a pair of synchronization codes are defined for each encoding system, and each synchronization code is positioned at the head of each scanning line of a picture signal, each of the synchronization codes have m 1 and m 2 number of continuous 0's inserted between a pair of 1's, a facsimile transmission station interpolates "1" for each series of (MIN(m i )-1) number of continuous 0's of the picture signal in order to distinguish the picture signal from synchronization codes where MIN(m i ) is the minimum value among m i and i is 1 or 2, and a receiving station eliminates the interpolated "1" to provide a clean output, wherein the value of (k) is switched according to the instantaneous quality of a communication line so that the value (k) when said quality is good is larger than that when said quality is bad.
Claim 2
Independent Claim
198 words
A method for controlling a facsimile system characterized in that the scanning lines of a picture signal are encoded so that (k) number of continuous scanning lines are encoded by a relative address encoding system and the next one scanning line is encoded by run length encoding system and that sequence is repeated, a pair of synchronization codes are defined for each encoding system, and each synchronization code is positioned at the head of each scanning line of a picture signal, each of the synchronization codes have m 1 and m 2 number of continuous 0's inserted between a pair of 1's, a facsimile transmission station interpolates "1" for each series of (MIN(m i )-1) number of continuous 0's of the picture signal in order to distinguish the picture signal from synchronization codes where MIN(m i ) is the minimum value among m i and i is 1 or 2, and a receiving station eliminates the interpolated "1" to provide a clean output, wherein the value of (k) is switched according to the instantaneous quality of a communication line so that the value (k) when said quality is good is larger than that when said quality is bad.
Claim 3
Dependent Claim
31 words
The invention as defined in claim 1, wherein the value of (k) when said quality is good is 4, and the value of (k) when said quality is bad is 2.
Claim 4
Dependent Claim
24 words
The invention as defined in claim 1, wherein said quality of an instantaneous communication line is provided as an SQD output of a modem.
Claim 5
Dependent Claim
415 words
A digital facsimile communication system having a transmitter and a receiver, a transmitter comprising; (a) a first input terminal for receiving a digitalized facsimile signal, (b) a second input terminal for receiving a timing pulse which appears in every scanning line, (c) a dummy code insertion circuit for encoding the input signal applied to the first input terminal so that the continuous (k) number of scanning lines are encoded to a relative address code and the next scanning line is encoded to a run length code and that sequence is repeated, and inserting in the output of the dummy code insertion circuit the signal pattern (10000 . . . 0001) which has a predetermined number of continuous 0's inserted between a pair of 1's, (d) a "1" insertion circuit for inserting the signal "1" in the output signal of the dummy code insertion circuit when said output signal has more continuous 0's than the predetermined number, (e) a synchronization signal generation circuit for alternately generating one of two synchronization patterns each of which has continuous 0's inserted between a pair of 1's, (f) a third input terminal for receiving an instantaneous quality of a communication line, (g) a pair of registers each storing the value (k 2 ) and (k 1 ) and the outputs of those registers being switched according to the input signal applied to the third input terminal, (h) a counter for counting the pulses applied to the second input terminal, (i) a comparator for comparing the output of said counter with one of the outputs of said registers and causing the selection of one of the relative address code and the run length code and the related synchronization patterns in the synchronization signal generation circuit, (j) a digital memory for storing the outputs of said "1" insertion circuit and said synchronization signal generation circuit, and (k) an output terminal connected to the output of said digital memory, and a receiver comprising (l) an input terminal for receiving the signal relating to signal on the output terminal of the transmitter through a communication line, (m) means for deleting the synchronization signal from the signal thus received in the input terminal, (n) means for deleting the signal "1" inserted in the "1" insertion circuit of the transmitter, (o) means for decoding the signal from a relative address code and a run length code, and (p) an output terminal connected to the output of the decoding means to provide the received digital facsimile signal.
Claim 6
Dependent Claim
415 words
A digital facsimile communication system having a transmitter and a receiver, a transmitter comprising; (a) a first input terminal for receiving a digitalized facsimile signal, (b) a second input terminal for receiving a timing pulse which appears in every scanning line, (c) a dummy code insertion circuit for encoding the input signal applied to the first input terminal so that the continuous (k) number of scanning lines are encoded to a relative address code and the next scanning line is encoded to a run length code and that sequence is repeated, and inserting in the output of the dummy code insertion circuit the signal pattern (10000 . . . 0001) which has a predetermined number of continuous 0's inserted between a pair of 1's, (d) a "1" insertion circuit for inserting the signal "1" in the output signal of the dummy code insertion circuit when said output signal has more continuous 0's than the predetermined number, (e) a synchronization signal generation circuit for alternately generating one of two synchronization patterns each of which has continuous 0's inserted between a pair of 1's, (f) a third input terminal for receiving an instantaneous quality of a communication line, (g) a pair of registers each storing the value (k 2 ) and (k 1 ) and the outputs of those registers being switched according to the input signal applied to the third input terminal, (h) a counter for counting the pulses applied to the second input terminal, (i) a comparator for comparing the output of said counter with one of the outputs of said registers and causing the selection of one of the relative address code and the run length code and the related synchronization patterns in the synchronization signal generation circuit, (j) a digital memory for storing the outputs of said "1" insertion circuit and said synchronization signal generation circuit, and (k) an output terminal connected to the output of said digital memory, and a receiver comprising (l) an input terminal for receiving the signal relating to signal on the output terminal of the transmitter through a communication line, (m) means for deleting the synchronization signal from the signal thus received in the input terminal, (n) means for deleting the signal "1" inserted in the "1" insertion circuit of the transmitter, (o) means for decoding the signal from a relative address code and a run length code, and (p) an output terminal connected to the output of the decoding means to provide the received digital facsimile signal.
Claim 7
Dependent Claim
51 words
The invention as defined in claim 4, wherein said two synchronization patterns are 10000001 which has six continuous 0's inserted between a pair of 1's, and 100000001 which has seven continuous 0's inserted between a pair of 1's, and value k 1 is 4 and the value k 2 is 2.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-19 | 1985-04-20 | 1985-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-19 | 1989-04-20 | 1989-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-19 | 1993-04-20 | 1993-10-20 | $7700.00 | Window Closed / Lapsed |