US4295192A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Row address memory map overlap
Assignee: Unisys Corp
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Filing: 1979-04-13
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Granted: 1981-10-13
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Expires: 1999-04-13
Abstract
Abstract There is described a map memory system with a time-multiplexed memory address bus wherein the mapping function is performed on the high order address bits in parallel with the output of the low order address bits on the time multiplex bus.
Inventors
- 👤 Brewster J. Porcella
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:25
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
142 words
A memory mapping apparatus comprising, a source of original address information wherein said original address information is comprised of a specified number of bits; memory map means connected to receive a first portion of said original address information directly from said source; multiplexer means connected to receive a different portion of said original address information directly from said source; memory means connected to said memory map means to concurrently supply memory information directly to said memory map means; and means connected between said memory map means and said multiplexer means and operative to supply map information to said multiplexer means from said memory map means, said multiplexer means providing new address information representative of said map information and said different portion of said original address information wherein said new address information includes mapped information from said memory via said memory map means.
Claim 2
Dependent Claim
142 words
A memory mapping apparatus comprising, a source of original address information wherein said original address information is comprised of a specified number of bits; memory map means connected to receive a first portion of said original address information directly from said source; multiplexer means connected to receive a different portion of said original address information directly from said source; memory means connected to said memory map means to concurrently supply memory information directly to said memory map means; and means connected between said memory map means and said multiplexer means and operative to supply map information to said multiplexer means from said memory map means, said multiplexer means providing new address information representative of said map information and said different portion of said original address information wherein said new address information includes mapped information from said memory via said memory map means.
Claim 3
Dependent Claim
33 words
The apparatus recited in claim 1 including: physical address drivers connected to selectively receive said first portion of said original address information from said source when said apparatus is in a non-mapping mode.
Claim 4
Dependent Claim
28 words
The apparatus recited in claim 1, wherein: said source includes input latch means for latching information from said source thereby to preserve the information in a useful format.
Claim 5
Dependent Claim
23 words
The apparatus recited in claim 1 including: map array driver means for selectively returning information to said memory means from said memory map.
Claim 6
Dependent Claim
40 words
The apparatus recited in claim 1, wherein said first portion of said original address information comprises the most significant bits in the information; and said different portion of said original address information comprises the least significant bits of the information.
Claim 7
Dependent Claim
41 words
The apparatus recited in claim 1, wherein: said memory map means and said multiplexer means are connected to receive the respective portions of the original address information at substantially the same time in relation to an operating cycle of the apparatus.
Claim 8
Dependent Claim
29 words
The apparatus recited in claim 3, wherein: said source includes bus-means connected to transfer information from said input latch means to said memory map means and said multiplexer means.
Claim 9
Dependent Claim
22 words
The apparatus recited in claim 1, wherein: said latch means produces output signals for selecting portions of the memory means for operation.
Claim 10
Dependent Claim
21 words
The apparatus recited in claim 1, wherein: said memory map means includes a plurality of memory circuits connected said memory means.
Claim 11
Independent Claim
78 words
The method of mapping a memory comprising: supplying information bits which represent a virtual memory address; applying some of the information bits directly to a multiplexer; concurently applying others of the information bits directly to a memory map array; decoding the others of the information bits in said memory map array and applying the decoded information to said multiplexer; and selectively multiplexing the information supplied to said multiplexer to produce an output signal representative of the mapping operation.
Claim 12
Independent Claim
78 words
The method of mapping a memory comprising: supplying information bits which represent a virtual memory address; applying some of the information bits directly to a multiplexer; concurently applying others of the information bits directly to a memory map array; decoding the others of the information bits in said memory map array and applying the decoded information to said multiplexer; and selectively multiplexing the information supplied to said multiplexer to produce an output signal representative of the mapping operation.
Claim 13
Dependent Claim
24 words
The apparatus recited in claim 1 wherein, said original address information may be in the form of a virtual address or a physical address.
Claim 14
Dependent Claim
15 words
The apparatus recited in claim 1 wherein said memory means include row and column addresses.
Claim 15
Dependent Claim
19 words
The apparatus recited in claim 12 wherein, said memory map effectively selects the column addresses in said memory means.
Claim 16
Dependent Claim
32 words
The method recited in claim 10 wherein, said decoding step includes applying said others of the information bits to a memory map array to select the decoded information from a memory means.
Claim 17
Dependent Claim
33 words
The method recited in claim 14 wherein said output signal is varied as a function of the information bits from said memory map array and said some of said information bits applied thereto.
Claim 18
Dependent Claim
29 words
The apparatus recited in claim 1 wherein, said first portion of said address information and said different portion of said address information comprise the entirety of said address information.
References Cited (Backward Citations)
US3854126A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-12 | 1985-04-13 | 1985-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-12 | 1989-04-13 | 1989-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-12 | 1993-04-13 | 1993-10-13 | $7700.00 | Window Closed / Lapsed |