US4295099A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peak detector
Assignee: Honeywell Inc
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Filing: 1979-09-05
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Granted: 1981-10-13
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Expires: 1999-09-05
Abstract
Abstract A peak detecting circuit includes apparatus wherein an analog input signal is applied to a pair of sample and hold circuit elements with the output of the two sample and hold circuits connected, respectively, to the two input terminals of a voltage level comparator. The output of the comparator changes phase when a peak value occurs in the input analog signal. The output of the comparator is then applied to the input of the phase change detector which, in turn, produces an output signal whenever the comparator indicates that a peak has occurred in the analog input signal.
Inventors
- 👤 Thomas E. Evans
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:55
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1532
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
107 words
A peak detector circuit comprising: input signal terminal means for connection to a source of analog signals, a first and second sample holding means, means connected to said input terminal means for applying successive samples of said analog signals to said first and second holding means alternately, comparator means connected to compare the magnitude of said signals stored in said holding means to produce a phase change signal on the occurrence of a peak value of said analog signal, and means connected to be responsive to said phase change signal from said comparator means to produce an output signal indicative of the occurrence of said peak value.
Claim 2
Dependent Claim
107 words
A peak detector circuit comprising: input signal terminal means for connection to a source of analog signals, a first and second sample holding means, means connected to said input terminal means for applying successive samples of said analog signals to said first and second holding means alternately, comparator means connected to compare the magnitude of said signals stored in said holding means to produce a phase change signal on the occurrence of a peak value of said analog signal, and means connected to be responsive to said phase change signal from said comparator means to produce an output signal indicative of the occurrence of said peak value.
Claim 3
Dependent Claim
60 words
A peak detector circuit as set forth in claim 1 wherein said means connected to said input terminal means comprises a first and a second switching means, said first switching means being connected between said terminal means and said first sample holding means, said second switching means being connected between said input terminal means and said second sample holding means.
Claim 4
Dependent Claim
21 words
A peak detector circuit as set forth in claim 2 wherein said first and second switching means are solid-state switching devices.
Claim 5
Dependent Claim
42 words
A peak detector circuit as set forth in claim 3 and including a control signal input means and control means connected to said first and second switching means responsive to the control signal for actuating said first and second switching means alternately.
Claim 6
Dependent Claim
120 words
A peak detector circuit as set forth in claim 3 and including a control signal input terminal for connection to a source of control pulses, a flip-flop circuit means having at toggle input connected to said control signal input terminal, said flip-flop circuit means having first and a second output terminal toggled into alternate energization responsive to said control signals, a first and second gate means each connected to be enabled by said control pulses and to be triggered, respectively, by said flip-flop circuit means, said first gate means having an output connected to control the actuation of said first switching means and said second gate means having an output connected to control the actuation of said second switching means.
Claim 7
Dependent Claim
74 words
A peak detector circuit as set forth in claim 5 wherein said means responsive to said phase change signal comprises a phase comparator having a first input connected to an output terminal of said comparator means and a second input connected to said second output terminal of said flip-flop circuit means for comparing the phase relationship of said signals input thereto and to produce an output signal in repsonse to a predetermined phase relationship.
Claim 8
Dependent Claim
21 words
A peak detector circuit at set forth in claim 6 wherein said predetermined phase relationship is a relationship of phase opposition.
Claim 9
Dependent Claim
19 words
A peak detector circuit as set forth in claim 6 wherein said phase comparator comprises an EXCLUSIVE OR gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-12 | 1985-04-13 | 1985-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-12 | 1989-04-13 | 1989-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-12 | 1993-04-13 | 1993-10-13 | $7700.00 | Window Closed / Lapsed |