US4292677A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-refreshed capacitor memory cell
Assignee: AT&T Inc
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Filing: 1980-01-07
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Granted: 1981-09-29
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Expires: 2000-01-07
Abstract
Abstract This invention involves a capacitor memory cell (C S ) of, typically the metal-oxide-semiconductor (MOS) capacitor type, which is accessed for reading and writing by means of an access network connected to the memory cell through a gating transistor (T 1 ), and which is provided with an independent refresh network for maintaining the memory state of the cell in the absence of an access writing signal. The refresh network includes a pair of MOSFET (Metal Oxide Semiconductor Field-Effect Transistors) transistors (T 2 , T 3 ) connected between the MOS capacitor and an A.C. refresh line which is independent of the electrical access network. Either a "full" or "empty" capacitor memory state, binary digital 1 or 0, respectively, is maintained without the need for interrupting the reading and writing of the MOS capacitor.
Inventors
- 👤 Harry J. Boll
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 00:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
106 words
Semiconductor apparatus including a network for refreshing the memory state of a semiconductor capacitor memory cell (C S ) comprising a first transistor (T 2 ), one of whose high current carrying terminals is DC coupled to one terminal of the capacitor, and another of whose high current terminals is DC coupled to a refresh line terminal (13.1), characterized in that, a low current carrying terminal of the first transistor (T 2 ) is DC coupled to one terminal of a two-terminal threshold resistive element (T 3 or R) whose other terminal is DC coupled to said one terminal of the first transistor (T 2 ).
Claim 2
Dependent Claim
106 words
Semiconductor apparatus including a network for refreshing the memory state of a semiconductor capacitor memory cell (C S ) comprising a first transistor (T 2 ), one of whose high current carrying terminals is DC coupled to one terminal of the capacitor, and another of whose high current terminals is DC coupled to a refresh line terminal (13.1), characterized in that, a low current carrying terminal of the first transistor (T 2 ) is DC coupled to one terminal of a two-terminal threshold resistive element (T 3 or R) whose other terminal is DC coupled to said one terminal of the first transistor (T 2 ).
Claim 3
Dependent Claim
12 words
Apparatus according to claim 1 in which all said couplings are ohmic.
Claim 4
Dependent Claim
36 words
Apparatus according to claims 1 or 2 which further includes a bypass capacitor arranged to provide AC coupling between said low current terminal of the first transistor (T 2 ) and said refresh line terminal (13.1).
Claim 5
Dependent Claim
137 words
Semiconductor apparatus including a random access MOS memory cell comprising: (a) a first MOS transistor, whose source is ohmically coupled to a bit line, and whose gate electrode is ohmically coupled to a work line; (b) an MOS storage capacitor, one of whose terminals is ohmically coupled to said bit line, the other of whose terminals is ohmically coupled to a voltage source terminal; (c) a second MOS transistor, whose source is ohmically coupled to said one terminal of the storage capacitor, and whose drain is ohmically coupled to a refresh line; and (d) a threshold resistor, one of whose high current terminals is ohmically coupled to said source of the second MOS transistor, and the other of whose high current terminals is ohmically coupled through an auxiliary MOS capacitor to said drain of the second transistor.
Claim 6
Dependent Claim
137 words
Semiconductor apparatus including a random access MOS memory cell comprising: (a) a first MOS transistor, whose source is ohmically coupled to a bit line, and whose gate electrode is ohmically coupled to a work line; (b) an MOS storage capacitor, one of whose terminals is ohmically coupled to said bit line, the other of whose terminals is ohmically coupled to a voltage source terminal; (c) a second MOS transistor, whose source is ohmically coupled to said one terminal of the storage capacitor, and whose drain is ohmically coupled to a refresh line; and (d) a threshold resistor, one of whose high current terminals is ohmically coupled to said source of the second MOS transistor, and the other of whose high current terminals is ohmically coupled through an auxiliary MOS capacitor to said drain of the second transistor.
References Cited (Backward Citations)
US4203159A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-28 | 1985-03-30 | 1985-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-28 | 1989-03-30 | 1989-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-28 | 1993-03-30 | 1993-09-29 | $7700.00 | Window Closed / Lapsed |