US4291330A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video signal processing circuit for eliminating an interfering signal
Assignee: Sony Corp
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Filing: 1979-04-24
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Granted: 1981-09-22
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Expires: 1999-04-24
Abstract
Abstract A video signal processing circuit eliminates an interfering signal that is included in a video signal, and is especially effective for eliminating an intefering signal that results from reproducing a video signal that is recorded in successive slant tracks on a recording medium, such as magnetic tape. In the video signal processing circuit, a delay line delays at least the luminance component of the video signal by a predetermined number of horizontal line intervals, a first subtracting circuit combines the delayed luminance component with the undelayed luminance component to produce a first difference signal, a limter limits the first difference signal and presents the limited first difference signal to a second subtracting circuit, where the latter signal is subtractively combined with the delayed luminance signal to produce an output signal free of interfering signals. In order to improve the performance of the processing circuit, a high pass filter and an adder circuit can be included to pass the high frequency portion of the first difference signal around the limiter. Alternatively, a deemphasizing circuit and a preemphasizing circuit can be respectively included in advance of, and following, the limiter.
Inventors
- 👤 Jun Hirai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:32
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/911; H04N9/00; H04N9/79; H04N9/7908; H04N9/7917; H04N9/87; H04N9/88
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
316 words
A video signal processing circuit for eliminating an interfering signal included in a video signal that is reproduced, from a recorded video signal recorded in successive parallel tracks on a record medium, by a transducer which scans one of said successive tracks, said interfering signal including crosstalk signals reproduced by said transducer from a track next adjacent the track being scanned, and said video signal comprising a frequency modulated luminance component whose carrier frequency varies by an amount 1/2(2 m+1)f H from the carrier frequency of the luminance component in the crosstalk signals reproduced from said track next adjacent the track being scanned, where m is an integer and f H is the horizontal line frequency, said circuit comprising: first frequency demodulating means for frequency demodulating said luminance component and providing a demodulated luminance component; delaying means for delaying said reproduced video signal for a predetermined number of horizontal line intervals to produce a delayed video signal; second frequency demodulating means for frequency demodulating the luminance component in said delayed video signal and providing a demodulated delayed luminance component; first combining means for combining said demodulated luminance component with said demodulated delayed luminance component, said first combining means producing a first difference signal representing the difference between said demodulated luminance component and said demodulated delayed luminance component; means for limiting said first diffference signal to produce a limited difference signal; high pass filter means coupled to said first combining means to pass a high frequency portion of said first difference signal; second combining means for additively combining said high frequency portion with said limited difference signal to provide a combined signal; and third combining means for combining said demodulated luminance signal with said combined signal to produce an output signal representing the difference between said demodulated luminance signal and said combined signal, whereby said third combining means produces said output signal free of said interfering signal.
Claim 2
Dependent Claim
316 words
A video signal processing circuit for eliminating an interfering signal included in a video signal that is reproduced, from a recorded video signal recorded in successive parallel tracks on a record medium, by a transducer which scans one of said successive tracks, said interfering signal including crosstalk signals reproduced by said transducer from a track next adjacent the track being scanned, and said video signal comprising a frequency modulated luminance component whose carrier frequency varies by an amount 1/2(2 m+1)f H from the carrier frequency of the luminance component in the crosstalk signals reproduced from said track next adjacent the track being scanned, where m is an integer and f H is the horizontal line frequency, said circuit comprising: first frequency demodulating means for frequency demodulating said luminance component and providing a demodulated luminance component; delaying means for delaying said reproduced video signal for a predetermined number of horizontal line intervals to produce a delayed video signal; second frequency demodulating means for frequency demodulating the luminance component in said delayed video signal and providing a demodulated delayed luminance component; first combining means for combining said demodulated luminance component with said demodulated delayed luminance component, said first combining means producing a first difference signal representing the difference between said demodulated luminance component and said demodulated delayed luminance component; means for limiting said first diffference signal to produce a limited difference signal; high pass filter means coupled to said first combining means to pass a high frequency portion of said first difference signal; second combining means for additively combining said high frequency portion with said limited difference signal to provide a combined signal; and third combining means for combining said demodulated luminance signal with said combined signal to produce an output signal representing the difference between said demodulated luminance signal and said combined signal, whereby said third combining means produces said output signal free of said interfering signal.
Claim 3
Dependent Claim
134 words
A video signal processing circuit for eliminating an interfering signal included in a video signal, said circuit comprising: delaying means for delaying said video signal for a predetermined number of horizontal line intervals to produce a delayed video signal; first combining means for combining said video signal with said delayed video signal, said first combining means producing a first difference signal representing the difference between said video signal and said delayed video signal; means for limiting amplitude excursions of said first difference signal to produce a limited difference signal; and second combining means for combining said video signal with said limited difference signal to produce an output signal representing the difference between said video signal and said limited difference signal, whereby said second combining means produces said output signal free of said interfering signal.
Claim 4
Dependent Claim
134 words
A video signal processing circuit for eliminating an interfering signal included in a video signal, said circuit comprising: delaying means for delaying said video signal for a predetermined number of horizontal line intervals to produce a delayed video signal; first combining means for combining said video signal with said delayed video signal, said first combining means producing a first difference signal representing the difference between said video signal and said delayed video signal; means for limiting amplitude excursions of said first difference signal to produce a limited difference signal; and second combining means for combining said video signal with said limited difference signal to produce an output signal representing the difference between said video signal and said limited difference signal, whereby said second combining means produces said output signal free of said interfering signal.
Claim 5
Dependent Claim
65 words
A video signal processing circuit according to claim 2, further comprising drop-out detecting means for detecting drop-out in said video signal, and drop-out compensating means including switching means controlled by said drop-out detecting means such that said delayed video signal from said delaying means is fed back, as said video signal, to said second combining means and to said delaying means whenever drop-out is detected.
Claim 6
Dependent Claim
19 words
A video signal processing circuit according to claim 2, further comprising attenuating means for attenuating said limited difference signal.
Claim 7
Dependent Claim
23 words
A video signal processing circuit according to claim 4, wherein said attenuating means attenuates to one-half the amplitude of said limited difference signal.
Claim 8
Dependent Claim
114 words
A video signal processing circuit according to claim 2, in which said video signal is reproduced, from a recorded video signal recorded in successive parallel tracks on a record medium, by a transducer which scans one of said successive tracks, said interfering signal includes crosstalk signals reproduced by said transducer from a track next adjacent the track being scanned, and said video signal comprises a frequency modulated luminance component whose carrier frequency varies by an amount 1/2(2 m+1)f H from the carrier frequency of the luminance component in the crosstalk signals reproduced from said track next adjacent the track being scanned, where m is an integer and f H is the horizontal line frequency.
Claim 9
Dependent Claim
63 words
A video signal processing circuit according to claim 6, further comprising: a first frequency demodulating means for frequency demodulating said luminance component and applying the demodulated luminance component to said first and second combining means; and second frequency demodulating means for frequency demodulating the luminance component in said delayed video signal and applying the demodulated delayed luminance component to said fist combining means.
Claim 10
Dependent Claim
62 words
A video signal processing circuit according to claim 7, further comprising: deemphasizing means coupled to said first combining means for deemphasizing said first difference signal and supplying a deemphasized first difference signal to said limiting means; and preemphasizing means coupled to said limiting means for preemphasizing said limited difference signal and supplying a preemphasized limited difference signal to said second combining means.
References Cited (Backward Citations)
US3872498A
Cited
US4012774A
Cited
US4003079A
Cited
US4052740A
Cited
US4093959A
Cited
US4074321A
Cited
US4143396A
Cited
US4167749A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |