Circuit arrangement for monitoring the state of signal systems, particularly traffic light signal systems

Claim 2

A circuit arrangement for monitoring the state of a signal system, comprising: a memory means storing a plurality of test signals corresponding to inadmissible signal states; an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state; and signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual signal with all test signals and emit said predetermined clock pulse sequence in response to equality of an actual state signal and a test signal.

Claim 3

The circuit arrangement of claim 1, wherein said signal comparison means comprises: a microprocessor connected to said memory means; and program means connected to and operable to control the operation of said microprocessor.

Claim 4

A circuit arrangement for monitoring the state of a signal system, comprising: a memory means storing a plurality of test signals corresponding to admissible actual states; an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state; and signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual signal with all test signals and emit said predetermined clock pulse sequence in response to inequality of an actual state signal and a test signal.

Claim 5

A circuit arrangement for monitoring the state of a signal system, comprising: a memory means storing a plurality of test signals corresponding to admissible actual states; an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state; and signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual signal with all test signals and emit said predetermined clock pulse sequence in response to inequality of an actual state signal and a test signal.

Claim 6

The circuit arrangement of claim 3, wherein said signal comparison means comprises: a microprocessor connected to said memory means; and program means connected to and operable to control the operation of said microprocessor.

Claim 7

A circuit arrangement for monitoring the state of a signal system, comprising: a memory means storing a plurality of test signals indicating test signal states, said memory means comprising first and second memories each storing a respective group of said test signals; an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state, said evaluation means comprising first and second evaluation devices each including an input for receiving the predetermined clock pulse sequence and an output for indicating an inadmissible actual signal state; and signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual state signal with all test signals and emit said predetermined clock pulse sequence in response to a comparison indicating an inadmissible actual state, said signal comparison means comprising first and second microprocessors connected to receive respective groups of actual state signals from said first inputs and connected to respective ones of said memories for receiving respective groups of test signals, and first and second program means connected to respective microprocessors for programming said microprocessors to compare the actual and test signals, each of said microprocessors connected to the input of a respective evaluation device.

Claim 8

A circuit arrangement for monitoring the state of a signal system, comprising: a memory means storing a plurality of test signals indicating test signal states, said memory means comprising first and second memories each storing a respective group of said test signals; an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state, said evaluation means comprising first and second evaluation devices each including an input for receiving the predetermined clock pulse sequence and an output for indicating an inadmissible actual signal state; and signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual state signal with all test signals and emit said predetermined clock pulse sequence in response to a comparison indicating an inadmissible actual state, said signal comparison means comprising first and second microprocessors connected to receive respective groups of actual state signals from said first inputs and connected to respective ones of said memories for receiving respective groups of test signals, and first and second program means connected to respective microprocessors for programming said microprocessors to compare the actual and test signals, each of said microprocessors connected to the input of a respective evaluation device.

Claim 9

The circuit arrangement of claim 5, wherein said first inputs of said signal comparison means comprises: a pulse generator for producing timing pulses; and a plurality of AND gates each including a signal input for receiving an actual state signal, a timing pulse input connected to said pulse generator, and an output connected to a respective input of the respective microprocessor.

Claim 10

The circuit arrangement of claim 6, wherein the signal system comprises signal transmitters fed by an electrical supply, and said evaluation devices each comprise: means connected in circuit between the electrical supply and the signal transmitters and operable to condition the transmitters to a predetermined state.

Claim 11

The circuit arrangement of claim 7, wherein said pulse generator comprises: means deriving the timing pulses from the electrical supply, the electrical supply being a conventional commercial a.c. supply.

Claim 12

The circuit arrangement of claim 8, wherein each of said microprocessors comprises: means for monitoring the outputs of said gates during the pauses between pulses.

Claim 13

The circuit arrangement of claim 9, wherein each of said microprocessors comprises: means for receiving a special test signal during a pulse pause and operable to provide a specific alarm signal.

Claim 14

The circuit arrangement of claim 10, wherein each of said microprocessors comprises: a special test signal input; and a special test signal output connected to said special test signal input of the other microprocessor.

Claim 15

The circuit arrangement of claim 11, wherein said special test signal input comprises: a plurality of OR gates each having a first input connected to the output of a respective AND gate, an output connected to a respective input of the respective microprocessor, and a second input connected to receive the special test signal from the other microprocessor.

Claim 16

The circuit arrangement of claim 12, comprising: first and second registers each including a signal input connected to a respective microprocessor and a plurality of stages each connected to said second input of an OR gate which is connected to the other respective microprocessor, for evaluation of the special test signal in the other respective microprocessor, during the pulse pauses of the actual state signals.

Claim 17

The circuit arrangement of claim 13, wherein each of said program means comprises a read only memory.

Claim 18

The circuit arrangement of claim 13, wherein each of said first and second memories comprises a random access memory.