US4286227A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor amplifying circuit for preventing the operation of an amplifying transistor in the quasi-saturation region
Assignee: Hitachi Ltd
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Filing: 1979-06-26
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Granted: 1981-08-25
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Expires: 1999-06-26
Abstract
Abstract The cut-off frequency of a transistor drops remarkably when the collector-emitter voltage of the transistor is driven into the quasi-saturation region of about 1 V. To prevent this problem, the collector-emitter voltage of the transistor is detected and compared with a predetermined reference voltage by comparison-limiting means. The comparison-limiting means limits the base current of the transistor and thus restricts the drop in the collector-emitter voltage. Limiting the voltage drop in this manner prevents the transistor from being driven into the quasi-saturation region. The reference voltage is set to the p-n junction voltage in the forward direction. Hence, the drop in the collector-emitter voltage is limited to a value near this reference voltage.
Inventors
- 👤 Tetsuo Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:53
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/3069; H03F3/3076; H03F1/00; H03F1/32; H03F1/34
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
117 words
A transistor circuit comprising: a first transistor; a second transistor of the same conduction type as said first transistor; a third transistor of the opposite conduction type to said first transistor and having its collector connected to the emitter of said first transistor; and level-shift diode means; said first transistor and said second transistor being connected with each other in a Darlington circuit arrangement; said second transistor forming the prestage of the Darlington circuit arrangement and said first transistor forming its post-stage; the base of said third transistor being connected to the collector of said first transistor; the base of said second transistor being connected to the emitter of said third transistor via said level-shift diode means.
Claim 2
Dependent Claim
117 words
A transistor circuit comprising: a first transistor; a second transistor of the same conduction type as said first transistor; a third transistor of the opposite conduction type to said first transistor and having its collector connected to the emitter of said first transistor; and level-shift diode means; said first transistor and said second transistor being connected with each other in a Darlington circuit arrangement; said second transistor forming the prestage of the Darlington circuit arrangement and said first transistor forming its post-stage; the base of said third transistor being connected to the collector of said first transistor; the base of said second transistor being connected to the emitter of said third transistor via said level-shift diode means.
Claim 3
Dependent Claim
85 words
The transistor circuit as defined in claim 1 wherein said first and second transistors each are a vertical type n-p-n transistor formed in a semiconductor integrated circuit, said third transistor is a substrate type p-n-p transistor using the p-type semiconductor substrate of said semiconductor integrated circuit as at least a part of its collector region, and the collector region of said first transistor and the base region of said third transistor are formed by a single n-type element-forming region disposed on said p-type semiconductor substrate.
Claim 4
Dependent Claim
43 words
The transistor circuit as defined in claim 2 wherein the collector region of said second transistor is further formed by said single n-type element-forming region so that the collector of said first transistor and the collector of said second transistor are commonly connected.
Claim 5
Dependent Claim
106 words
The transistor circuit as defined in claim 1 wherein said transistor circuit further includes: an initial stage differential amplifying circuit; collector load means for said first and second Darlington-connected transistors; a B-class push-pull circuit; and a negative feed-back circuit interposed between the output of said B-class push-pull circuit and either one of two inputs of said initial stage differential amplifying circuit; said first and second transistors in the Darlington circuit arrangement being driven by the output of said initial stage differential amplifying circuit and forming, together with said collector load means, a large amplitude A-class transistor amplifying circuit so as to drive said B-class push-pull circuit.
Claim 6
Dependent Claim
104 words
A transistor circuit comprising: a first transistor and a second transistor, each having of the n-p-n type; a p-n-p type third transistor having its collector connected to the emitter of said first transistor; and level-shift diode means; said first and second transistors being connected with each other in a Darlington circuit arrangement; said second transistor forming the prestage of the Darlington circuit arrangement and said first transistor forming its post-stage; the collector of said first transistor being connected to the base of said third transistor; the base of said second transistor being connected to the emitter of said third transistor via said level-diode means.
Claim 7
Dependent Claim
104 words
A transistor circuit comprising: a first transistor and a second transistor, each having of the n-p-n type; a p-n-p type third transistor having its collector connected to the emitter of said first transistor; and level-shift diode means; said first and second transistors being connected with each other in a Darlington circuit arrangement; said second transistor forming the prestage of the Darlington circuit arrangement and said first transistor forming its post-stage; the collector of said first transistor being connected to the base of said third transistor; the base of said second transistor being connected to the emitter of said third transistor via said level-diode means.
Claim 8
Dependent Claim
87 words
A transistor circuit comprising: a transistor; and a detection-comparison circuit for detecting the collector-emitter voltage of said transistor and for comparing said collector-emitter voltage with a reference voltage, wherein said reference voltage is set to a voltage corresponding to approximately twice the p-n junction voltage in the forward direction, said detection-comparison circuit including means for limiting the base current of said transistor before said transistor is driven to the quasi-saturation region and for limiting the drop of said collector-emitter voltage of said transistor near said reference voltage.
Claim 9
Dependent Claim
87 words
A transistor circuit comprising: a transistor; and a detection-comparison circuit for detecting the collector-emitter voltage of said transistor and for comparing said collector-emitter voltage with a reference voltage, wherein said reference voltage is set to a voltage corresponding to approximately twice the p-n junction voltage in the forward direction, said detection-comparison circuit including means for limiting the base current of said transistor before said transistor is driven to the quasi-saturation region and for limiting the drop of said collector-emitter voltage of said transistor near said reference voltage.
Claim 10
Dependent Claim
55 words
A transistor circuit comprising: a transistor; and a circuit for detecting the collector-emitter voltage of said transistor and for comparing the detected voltage with a reference voltage, said detection-comparison circuit including means for limiting the base current of said transistor so as to limit the drop of said collector-emitter voltage of said transistor above IV.
Claim 11
Dependent Claim
55 words
A transistor circuit comprising: a transistor; and a circuit for detecting the collector-emitter voltage of said transistor and for comparing the detected voltage with a reference voltage, said detection-comparison circuit including means for limiting the base current of said transistor so as to limit the drop of said collector-emitter voltage of said transistor above IV.
Claim 12
Dependent Claim
23 words
The transistor circuit as defined in claim 7, wherein said detection-comparison circuit limits the drop of said collector-emitter voltage to 1.33 V, approximately.
Claim 13
Dependent Claim
131 words
A transistor circuit comprising: a first transistor; a first p-n junction device, the one terminal of which is connected to the base of said first transistor; a second p-n junction device, the one terminal of which is connected to the other terminal of said first p-n junction device; and a control transistor of the opposite conduction type to said first transistor, the emitter of which is connected to the other terminal of said second p-n junction device; wherein said first p-n junction device and said second p-n junction device are connected in the forward directions between said emitter of said control transistor and said base of said first transistor, the base and the collector of said control transistor being connected to the collector and the emitter of said first transistor, respectively.
Claim 14
Dependent Claim
131 words
A transistor circuit comprising: a first transistor; a first p-n junction device, the one terminal of which is connected to the base of said first transistor; a second p-n junction device, the one terminal of which is connected to the other terminal of said first p-n junction device; and a control transistor of the opposite conduction type to said first transistor, the emitter of which is connected to the other terminal of said second p-n junction device; wherein said first p-n junction device and said second p-n junction device are connected in the forward directions between said emitter of said control transistor and said base of said first transistor, the base and the collector of said control transistor being connected to the collector and the emitter of said first transistor, respectively.
References Cited (Backward Citations)
US3482111A
Cited
US4118640A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-24 | 1985-02-23 | 1985-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-24 | 1989-02-23 | 1989-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-24 | 1993-02-23 | 1993-08-25 | $7700.00 | Window Closed / Lapsed |