Repeating station for use in digital data communications link

Claim 2

For use in a digital data communication link, a repeating station for selectively forwarding serially transmitted digital data including incoming messages of defined length and identifiable beginning comprising: (a) detecting means for receiving incoming digital data and for providing data signals representative thereof; (b) a free running internal clock for providing clocking signals at a predetermined frequency which in a multiple of the bit rate of said transmitted digital data; (c) retiming logic responsive to said clocking signals for generating timing signals; (d) modulating means substantially instantaneously responsive to said data signals and said timing signals to reconstruct the incoming digital data in a time relationship governed by said clocking means to thereby provide reconstructed digital data signals; and, (e) transmitting means for transmitting said reconstructed digital data signals on said data communication link.

Claim 3

The invention in accordance with claim 1 further including means responsive to prescribed bit patterns of said reconstructed digital data to inhibit the operation of said transmitting means.

Claim 4

The invention in accordance with claim 1 further including means responsive to a prescribed bit pattern of said reconstructed digital data to initialize said timing logic.

Claim 5

The invention in accordance with claim 1 further including logic means responsive to an externally supplied inverting signal to selectively invert the state of individual bits of said reconstructed digital data.

Claim 6

The invention in accordance with claim 4 further including means to supply said reconstructed digital data signals to external equipment supplying said inverting signal.

Claim 7

The invention in accordance with claim 1 wherein said detecting means comprises first and second comparators responsive, respectively, to relatively positive and negative going incoming digital data.

Claim 8

The invention in accordance with claim 1 wherein said retiming logic comprises a recycling counter means for counting said clock pulses and for providing a designated output signal to said modulating means during a prescribed portion of each cycle of said counter.

Claim 9

The invention in accordance with claim 1 further including means to supply said reconstructed digital data signals as synchronizing clock signals to external equipment associated with said repeating station.

Claim 10

The invention in accordance with claim 1 further including means to supply said reconstructed digital data signals as synchronizing clock signals to external equipment associated with said repeating station and wherein said repeating station further includes logic means responsive to an inverting signal supplied by the external equipment to selectively invert the state of individual bits of said reconstructed digital data.

Claim 11

A repeating station for a data communications link over which digital messages, comprised of relative positive and negative going incoming signals of a frequency, of defined length and having an identifiable beginning are transmitted comprising: (a) means for detecting said relative positive and negative going signals and for providing output signals indicative thereof; (b) latch means responsive to said output signals for providing latch signals alternately with the occurrence of said output signals; (c) clock means for providing clock signals at a frequency equal to a multiple of the frequency of said positive and negative going signals; (d) first recycling counter means for repetitively counting a predetermined number of clock signals and for providing a trigger signal during a defined portion of each count; (e) first bistable means responsive to said latch signals and said trigger signal for providing complementary timing signals and for providing a designated one of said signals upon the occurrence of a reset signal; (f) first logic means for providing said reset signal in response to a designated count of said first counter means; (g) second and third recycling counter means for counting clock signals except during the occurrence of a respective one of said complementary timing signals, said second and third counter means being held in the zero condition during the occurrence of its respective timing signal; (h) second and third logic means responsive respectively to designated contents of said second and third counter means for providing output signals representative of said incoming signals; (i) transmitter means for selectively applying said output signals to said data link; (j) intermessage and error detector means responsive to either of two prescribed patterns of said outgoing signals and said complementary timing signals to generate an inhibit signal to inhibit said transmitter means and to a one of said prescribed patterns and a one of said complementary timing signals to provide a second signal to identify the beginning of a message; and, (k) second bistable means operative to generate a reset pulse for resetting said first recycling counter means to a fixed content in response to said signal, said reset signal and a one of said latch signals.

Claim 12

A repeating station for a data communications link over which digital messages, comprised of relative positive and negative going incoming signals of a frequency, of defined length and having an identifiable beginning are transmitted comprising: (a) means for detecting said relative positive and negative going signals and for providing output signals indicative thereof; (b) latch means responsive to said output signals for providing latch signals alternately with the occurrence of said output signals; (c) clock means for providing clock signals at a frequency equal to a multiple of the frequency of said positive and negative going signals; (d) first recycling counter means for repetitively counting a predetermined number of clock signals and for providing a trigger signal during a defined portion of each count; (e) first bistable means responsive to said latch signals and said trigger signal for providing complementary timing signals and for providing a designated one of said signals upon the occurrence of a reset signal; (f) first logic means for providing said reset signal in response to a designated count of said first counter means; (g) second and third recycling counter means for counting clock signals except during the occurrence of a respective one of said complementary timing signals, said second and third counter means being held in the zero condition during the occurrence of its respective timing signal; (h) second and third logic means responsive respectively to designated contents of said second and third counter means for providing output signals representative of said incoming signals; (i) transmitter means for selectively applying said output signals to said data link; (j) intermessage and error detector means responsive to either of two prescribed patterns of said outgoing signals and said complementary timing signals to generate an inhibit signal to inhibit said transmitter means and to a one of said prescribed patterns and a one of said complementary timing signals to provide a second signal to identify the beginning of a message; and, (k) second bistable means operative to generate a reset pulse for resetting said first recycling counter means to a fixed content in response to said signal, said reset signal and a one of said latch signals.

Claim 13

The invention in accordance with claim 10 further including logic means responsive to an externally applied inverting signal for selectively inverting the states of said outgoing signals.

Claim 14

The invention in accordance with claim 10 wherein said reset signal from said first logic means is generated in response to said fixed count of said first counter means.

Claim 15

The invention in accordance with claim 10 wherein said detection means comprises first and second comparators responsive, respectively, to positive and negative going incoming signals.

Claim 16

The invention in accordance with claim 10 wherein each of said counter means has four stages only one of which is changed with each occurrence of a clock signal.

Claim 17

The invention in accordance with claim 10 wherein said intermessage and error detector means includes means to generate said inhibit signal in response to a specified consecutive number of like outgoing pulses of either relative polarity and to generate said second signal only in response to a specified consecutive number of like outgoing pulses of a one of said relative polarities.

Claim 18

The invention in accordance with claim 10 further including means to supply the output signals of said second and third logic means as synchronizing clock signals to external equipment associated with said repeating station.

Claim 19

The invention in accordance with claim 10 further including means to supply the output signals of said second and third logic means as synchronizing clock signals to external equipment associated with said repeating station and wherein said repeating station further includes logic means responsive to an inverting signal supplied by an external equipment to selectively invert the states of said outgoing signals.