Successive approximation S/D converter with inherent quantization error centering

Claim 1

In a successive-approximation sampling resolver or synchro to digital converter which converts analog signals representing sin θ and cos θ to an n-bit digital signal representing θ, a comparison network which comprises: means for inverting the cos θ input to generate a -cos θ input; first switching means having a first switching path which connects the sin θ input to a first switch output and the -cos θ input to a second switch output and having a second switching path which connects the cos θ output to the first switch output and the sin θ output to the second switch output; first error centering means for multiplying the first switch output voltage by the 1/2 LSB ratio to generate a first error centering output; quadrant comparator means having the cos θ input as an inverting input and having the first error centering output as a non-inverting input; first attenuation means for attenuating the first switch output; second attenuation means for attenuating the second switch output; a binary weighted resistance ladder having n-2 resistive steps; second switching means for selectively connecting the first or second attenuated switch outputs to each of the steps of said resistance ladder; second error centering means for multiplying the second switch output by the 1/2 LSB ratio thereby generating a second error centering output; third error centering means having as an input the attenuated first switch output and having as an output a resistance ladder compensating voltage; ladder comparator means having as an inverting input the sum of said resistance ladder outputs and the compensating voltage and having as a non-inverting input the second error centering output; and logic means for initially connecting the first switching path, decoding the initial output of the quadrant comparator means and the ladder comparator means to determine the two most significant bits of θ and then connecting either the first or second switching paths, and thereafter successively connecting steps of said resistance ladder to the second attenuated switch output and sensing the output of the ladder comparator means to determine the n-2 less significant bits of θ.

Claim 10

A method for converting analog signals representing sin θ and cos θ to an n-bit digital signal representing θ, which comprises: inverting the cos θ input to generate a -cos θ input; initially connecting the sin θ input to a first switch output and the -cos θ input to a second switch output; generating a first error centering voltage which equals the first switch output multiplied by the 1/2 LSB ratio; subtracting the cos θ input from the first error centering voltage to generate a quadrant comparator voltage; attenuating the first switch output to produce a first attenuated switch output; attenuating the second switch output to produce a second attenuated switch output; initially connecting the first attenuated switch output to the steps of a binary weighted resistance ladder; generating a second error centering voltage which equals the second switch output multiplied by the 1/2 LSB ratio; shunting said resistance ladder with a large resistance connected to the first attenuated switch output to generate a resistance ladder compensating voltage; summing said resistance ladder output voltages and the resistance ladder compensating voltage to generate a summed voltage; subtracting the summed voltage from the second error centering voltage to generate a ladder comparator output voltage; decoding the quadrant comparator output and the ladder comparator output to determine the quadrant in which θ lies, thereby determining the two most significant bits of the digital output; connecting the sin θ input to the first switch output and the -cos θ input to the second switch output if θ is in the first or third quadrant, otherwise connecting the cos θ input to the first switch output and the sin θ input to the second switch output; successively switching the steps of said resistance ladder to the second switch output; and testing the polarity of the ladder comparator output voltage to determine the value of the n-2 less significant bits of the digital output.

Claim 11

A method for converting analog signals representing sin θ and cos θ to an n-bit digital signal representing θ, which comprises: inverting the cos θ input to generate a -cos θ input; initially connecting the sin θ input to a first switch output and the -cos θ input to a second switch output; generating a first error centering voltage which equals the first switch output multiplied by the 1/2 LSB ratio; subtracting the cos θ input from the first error centering voltage to generate a quadrant comparator voltage; attenuating the first switch output to produce a first attenuated switch output; attenuating the second switch output to produce a second attenuated switch output; initially connecting the first attenuated switch output to the steps of a binary weighted resistance ladder; generating a second error centering voltage which equals the second switch output multiplied by the 1/2 LSB ratio; shunting said resistance ladder with a large resistance connected to the first attenuated switch output to generate a resistance ladder compensating voltage; summing said resistance ladder output voltages and the resistance ladder compensating voltage to generate a summed voltage; subtracting the summed voltage from the second error centering voltage to generate a ladder comparator output voltage; decoding the quadrant comparator output and the ladder comparator output to determine the quadrant in which θ lies, thereby determining the two most significant bits of the digital output; connecting the sin θ input to the first switch output and the -cos θ input to the second switch output if θ is in the first or third quadrant, otherwise connecting the cos θ input to the first switch output and the sin θ input to the second switch output; successively switching the steps of said resistance ladder to the second switch output; and testing the polarity of the ladder comparator output voltage to determine the value of the n-2 less significant bits of the digital output.