Charge transfer apparatus

Claim 1

In combination, a first plurality of N charge transfer shift registers, said first plurality of shift registers formed in parallel on a first substrate and consecutively numbered from 1 to N, each shift register including n identical stages, each stage including a plurality of electrodes, said n identical stages of each shift register divided into a first part and a second part, the first shift register including n stages in the first part and zero stages in the second part, the number of stages included in the second parts of said shift registers between said first and said N th shift register varying linearly with shift register number from said first to said N th shift register with each successively numbered shift register having p stages more than the previously numbered shift register, the N th shift register including m stages in the second part and n-m stages in the first part where m is p stages less than n-m, whereby the number n of stages in each shift register equals (2N-1) p, a first set of conductors, each interconnecting respective electrodes of the stages of the first parts of said first plurality of shift registers, a second set of conductors, each interconnecting respective electrodes of the stages of the second parts of said first plurality of shift registers, a second plurality of N charge transfer shift registers, said second plurality of shift registers formed in parallel on a second substrate and consecutively numbered from 2N to N+1, each shift register including n identical stages, each stage including a plurality of electrodes, said n identical stages of each shift register divided into a first part and a second part, the 2N th shift register including n stages in the first part and zero stages in the second part, the number of stages included in the second parts of said shift registers between said 2N th and said (N+1) th shift register varying linearly with shift register number from said 2N th to said (N+1) th shift register with successively numbered shift registers having p stages more than the previously numbered shift register, the (N+1) th shift register including m stages in the second part and n-m stages in the first part where m is p stages less than n-m, whereby the number n of stages in each shift register equals (2N-1) p, each of said first set of conductors interconnecting respective electrodes of the stages of the second parts of said second plurality of shift registers, each of said second set of conductors interconnecting respectively electrodes of the stages of the first parts of said second plurality of shift registers, means for providing 2N analog signals consecutively numbered from 1 to 2N, signals 1 to N constituting a first plurality of analog signals and signals 2N to N+1 constituting a second plurality of signals, means for inverting each of the signals of said second plurality of signals, means for introducing a first plurality of series of packets of charge into said first plurality of shift registers, each series representing successive samples of a respective one of said first plurality of analog signals, means for introducing a second plurality of series of packets of charge into said second plurality of shift registers, each series representing successive samples of a respective one of said inverted signals of second plurality of analog signals, means for applying a first set of clocking voltages of a first frequency to said first set of conductors and for applying a second set of clocking voltages of a second frequency to said second set of conductors, means for detecting and summing the outputs of said first plurality of shift registers to obtain a first sum output, means for detecting and summing the outputs of said second plurality of shift registers to obtain a second sum output, and means for obtaining an output representing the difference of said first sum output and said second sum output.