CCD memory retrieval system

Claim 1

A memory system for use in a data processing system in which a central processor generates a sequence of requested read and write instructions including the address of the data to be accessed over a common bus, said system comprising: a first operating main memory unit coupled to said common bus for storing data to be accessed by the central processor over said common bus; a plurality of buffer memory units each having a higher operational speed than said first main memory unit and coupled to said main memory unit and the common bus for storing a portion of the data stored in said main memory unit; an address register for each of said buffer memory units coupled to the common bus for storing the addresses of the data stored in an associated buffer memory unit; comparison means for each of said buffer memory units coupled to the common bus and the address registers of an associated buffer memory unit for comparing the address of the requested data appearing on the common bus with the addresses stored in its coupled address register for outputting a first control signal upon finding a coincidence in one of said buffer memory units and a second control signal upon finding no coincidence in any of the buffer memory units; a first bi-stable means coupled to the output of each of said comparision means, said common bus and said address registers for outputting a first memory enabling signal in response to the generation of said first control signal enabling the buffer memory unit in which the coincidence was found to be accessed by the address of the requested data appearing on the common bus, and enabling said address registers to store the address of the data written into said buffer memory units, said first bi-stable means being further operated in response to said second control signal and to the generation of the next sequential read and write instruction to output said first memory enabling signal to the buffer unit not previously accessed thereby enabling said buffer unit to receive the requested data from the main memory unit for storage therein; and a second bi-stable means coupled to the output of each of said comparison means for outputting a third control signal in response to the generation of said second control signal, said system further including a third bi-stable means coupled to the output of said second bi-stable means for outputting a fourth control signal initiating the transfer of the requested data from the main memory unit to one of said buffer memory units in response to receiving said third control signal.